counter_16_bits.tan.rpt

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[2]  ; lpm_counter:counter_out_rtl_0|dffs[2]  ; Clk_65536Hz ; Clk_65536Hz ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[1]  ; lpm_counter:counter_out_rtl_0|dffs[1]  ; Clk_65536Hz ; Clk_65536Hz ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[0]  ; lpm_counter:counter_out_rtl_0|dffs[0]  ; Clk_65536Hz ; Clk_65536Hz ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+----------------------------------------+----------------------------------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------------------------------+
; tco                                                                                                        ;
+-------+--------------+------------+----------------------------------------+-----------------+-------------+
; Slack ; Required tco ; Actual tco ; From                                   ; To              ; From Clock  ;
+-------+--------------+------------+----------------------------------------+-----------------+-------------+
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[15] ; counter_out[15] ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[14] ; counter_out[14] ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[13] ; counter_out[13] ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[12] ; counter_out[12] ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[11] ; counter_out[11] ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[10] ; counter_out[10] ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[9]  ; counter_out[9]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[8]  ; counter_out[8]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[7]  ; counter_out[7]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[6]  ; counter_out[6]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[5]  ; counter_out[5]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[4]  ; counter_out[4]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[3]  ; counter_out[3]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[2]  ; counter_out[2]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[1]  ; counter_out[1]  ; Clk_65536Hz ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[0]  ; counter_out[0]  ; Clk_65536Hz ;
+-------+--------------+------------+----------------------------------------+-----------------+-------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Jul 19 20:36:46 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter_16_bits -c counter_16_bits
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk_65536Hz" is an undefined clock
Info: Clock "Clk_65536Hz" has Internal fmax of 172.41 MHz between source register "lpm_counter:counter_out_rtl_0|dffs[0]" and destination register "lpm_counter:counter_out_rtl_0|dffs[15]" (period= 5.8 ns)
    Info: + Longest register to register delay is 3.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 17; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[0]'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[15]'
        Info: Total cell delay = 2.600 ns ( 70.27 % )
        Info: Total interconnect delay = 1.100 ns ( 29.73 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clk_65536Hz" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'Clk_65536Hz'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[15]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "Clk_65536Hz" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'Clk_65536Hz'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC17; Fanout = 17; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tco from clock "Clk_65536Hz" to destination pin "counter_out[15]" through register "lpm_counter:counter_out_rtl_0|dffs[15]" is 2.800 ns
    Info: + Longest clock path from clock "Clk_65536Hz" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'Clk_65536Hz'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[15]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[15]'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'counter_out[15]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jul 19 20:36:47 2006
    Info: Elapsed time: 00:00:02