class.ptf

ISP的IP核

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#:-: date: 2003.01.13 16:19:57
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# This is a hardware interface to an exteral isp1161a1 USB H/D.
# 
# This adds an avalon_tristate-type slave to your system, representing
# the bus-interface to the external device.
# 
# In the past, this component "came with" the plugs networking
# library.  No more.  Now this component "comes with" a minimal API
# that makes it visible to plugs, but plugs is delivered separately
# as a software component.
# 
   CLASS mtx_avalon_isp1161a1
   {
      USER_INTERFACE 
      {
         USER_LABELS 
         {
            name = "isp1161a1 Interface (USB)";
            description = "Interface to external 10/100Mb MAC/PHY chip: SMSC isp1161a1";
            technology = "USB,EP1S10 Nios Development Board Stratix Edition,EP1S40 Nios Development Board Stratix Pro Edition,EP1C20 Nios Development Board Cyclone Edition,EP2S60 Nios Development Board Stratix II Edition,EP2S60 DSP Board Stratix II Edition";
            license = "full";
         }
         LINKS 
         {
            LINK help
            {
               title = "Nios USB Development Kit User Guide";
               url = "http://www.mtx.com/literature/ug/ug_niosedk.pdf";
            }
            LINK plugs
            {
               url="http://www.mtx.com/literature/manual/mnl_plugs.pdf";
               title="Plugs USB Library";
            }                            
            LINK StratixII_2S60_Manual
            {
               title="Manual for Nios 2s60 Stratix II Board";
               url="http://www.mtx.com/literature/manual/mnl_nios2_board_stratixII_2s60.pdf";
            }
            LINK StratixII_2S60_Schematics
            {
               title="Schematics for Nios 2s60 Stratix II Board";
               url="nios_stratixII_2s60/nios_2s60_board_schematic.pdf";
            }
            LINK Stratix_1S40_Manual
            {
               title="Manual for Nios 1s40 Stratix Board";
               url="http://www.mtx.com/literature/manual/mnl_nios2_board_stratix_1s40.pdf";
            }
            LINK Stratix_1S40_Schematics
            {
               title="Schematics for Nios 1s40 Stratix Board";
               url="nios_stratix_1s40/nios_1s40_board_schematic.pdf";
            }
            LINK Stratix_1S10_Manual
            {
               title="Manual for Nios 1s10 Stratix Board";
               url="http://www.mtx.com/literature/manual/mnl_nios2_board_stratix_1s10.pdf";
            }
            LINK Stratix_1S10_Schematics
            {
               title="Schematics for Nios 1s10 Stratix Board";
               url="nios_stratix_1s10/nios_1s10_board_schematic.pdf";
            }
            LINK Cyclone_Manual
            {
               title="Manual for Nios 1c20 Cyclone Board";
               url="http://www.mtx.com/literature/manual/mnl_nios2_board_cyclone_1c20.pdf";
            }
            LINK Cyclone_Schematics
            {
               title="Schematics for Nios 1c20 Cyclone Board";
               url="nios_cyclone_1c20/nios_1c20_board_schematic.pdf";
            }
         }
         WIZARD_UI default
         {
            title = "USB Adapter - {{ $MOD }}";
            CONTEXT 
            {
               SPW = "SLAVE s1/PORT_WIRING";
               CONSTANTS = "WIZARD_SCRIPT_ARGUMENTS/CONSTANTS";
               SBI = "SLAVE s1/SYSTEM_BUILDER_INFO";
            }
            GROUP 
            {
               align = "left";
               title = "Presets";
               RADIO 
               {
                  id = "devboard";
                  title = "isp1161a1 MAC/PHY On Development Board";
                  font = "bold";
                  key = "b";
                  GROUP 
                  {
                     indent = "30";
                     TEXT 
                     {
                        title = "
Registers are aligned on half-word boundaries. <BR>
The full 14-bit address width of the chip is used. <BR>
The 8 registers can be accessed at locations <BR>
base+0x0300 through base+0x030f. <BR>
<BR>
<em>This is how the isp1161a1 USB Peripheral is <BR>
wired on the Nios Development Board, Stratix Edition <BR>
and Nios Development Board, Cyclone Edition. </em> <br>";
                        font = "small";
                     }
                  }
                  DATA 
                  {
                     $SPW/PORT address/width = "2";
                     $SPW/PORT data/width = "16";
                     $SBI/Data_Width = "16";
                     $SBI/Address_Width = "2";
                  }
               }
            }
         }
      }
      ASSOCIATED_FILES 
      {
         Add_Program = "default"; # No generator program, because this is a system-external component:
         Generator_Program = "--none--";
         Edit_Program = "default";
      }
      MODULE_DEFAULTS 
      {
         class = "mtx_avalon_isp1161a1";
         class_version = "1.0";
         SYSTEM_BUILDER_INFO 
         {
            Instantiate_In_System_Module = "0";
            Wire_Test_Bench_Values = "1";
            Is_Enabled = "1";
         }
         SLAVE s1
         {
            SYSTEM_BUILDER_INFO 
            {
               Instantiate_In_System_Module = "0";
               Is_Enabled = "1";
               Is_Bus_Master = "0";
               Bus_Type = "avalon_tristate";
               Uses_Tri_State_Data_Bus = "1";
               Address_Alignment = "native";
               Address_Width = "2";
               Data_Width = "16";
               Has_IRQ = "1";
               Read_Wait_States = "175ns";
               Write_Wait_States = "175ns";
               Setup_Time = "10ns";
               Hold_Time = "5ns";
               Is_Memory_Device = "0";
               Date_Modified = "2002.03.19.10:51:51";
               IRQ_Number = "--unknown--";
               Base_Address = "--unknown--";
               Tri_State_Data_Bus = "--unknown--";
            }
            PORT_WIRING 
            {
               PORT irq
               {
                  direction = "output";
                  width = "1";
                  type = "irq_n";
                  test_bench_value = "0";
               }
               PORT address
               {
                  is_shared = "1";
                  direction = "input";
                  width = "2";
                  type = "address";
               }
               PORT data
               {
                  is_shared = "1";
                  direction = "inout";
                  width = "16";
                  type = "data";
               }
               PORT cs_n
               {
                  direction = "input";
                  width = "1";
                  type = "chipselect_n";
               }
               PORT iow_n
               {
                  direction = "input";
                  width = "1";
                  type = "write_n";
               }
               PORT ior_n
               {
                  direction = "input";
                  width = "1";
                  type = "read_n";
               }
            }
         }
      }
   }