class.ptf.bak

ISP的IP核

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#:-: date: 2003.01.13 16:19:57
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# This is a hardware interface to an exteral dm9000 10/100
# Ethernet PHY/MAC.
# 
# This adds an avalon_tristate-type slave to your system, representing
# the bus-interface to the external device.
# 
# This component "comes with" a minimal API.
# 
   CLASS mtx_avalon_isp1161a1
   {
      USER_INTERFACE 
      {
         USER_LABELS 
         {
            name = "isp1161a1 Interface (Ethernet)";
            description = "Interface to external 10/100Mb MAC/PHY chip: Davicom isp1161a1";
            technology = "Ethernet, CMB (Cyclone Mother Board) 1.0";
            license = "full";
         }
         LINKS 
         {
            LINK help
            {
               title = "Nios Ethernet Development Kit User Guide";
               url = "http://www.altera.com/literature/ug/ug_niosedk.pdf";
            }
            LINK Stratix_1S40_Manual
            {
               title="Manual for Nios 1s40 Stratix Board";
               url="http://www.altera.com/literature/manual/mnl_nios2_board_stratix_1s40.pdf";
            }
            LINK Stratix_1S40_Schematics
            {
               title="Schematics for Nios 1s40 Stratix Board";
               url="nios_stratix_1s40/nios_1s40_board_schematic.pdf";
            }
            LINK Stratix_1S10_Manual
            {
               title="Manual for Nios 1s10 Stratix Board";
               url="http://www.altera.com/literature/manual/mnl_nios2_board_stratix_1s10.pdf";
            }
            LINK Stratix_1S10_Schematics
            {
               title="Schematics for Nios 1s10 Stratix Board";
               url="nios_stratix_1s10/nios_1s10_board_schematic.pdf";
            }
            LINK Cyclone_Manual
            {
               title="Manual for Nios 1c20 Cyclone Board";
               url="http://www.altera.com/literature/manual/mnl_nios2_board_cyclone_1c20.pdf";
            }
            LINK Cyclone_Schematics
            {
               title="Schematics for Nios 1c20 Cyclone Board";
               url="nios_cyclone_1c20/nios_1c20_board_schematic.pdf";
            }
         }
         WIZARD_UI default
         {
            title = "Ethernet Adapter - {{ $MOD }}";
            CONTEXT 
            {
               SPW = "SLAVE s1/PORT_WIRING";
               CONSTANTS = "WIZARD_SCRIPT_ARGUMENTS/CONSTANTS";
               SBI = "SLAVE s1/SYSTEM_BUILDER_INFO";
            }
            GROUP 
            {
               align = "left";
               title = "Presets";
               RADIO 
               {
                  title = "isp1161a1 MAC/PHY On CMB 1.0";
                  font = "bold";
                  key = "b";
                  GROUP 
                  {
                     indent = "30";
                     TEXT 
                     {
                        title = "
Registers are 8-bit. <BR>
Data-Bus is 16-bit. <BR>
<BR>
<em>This is how the DM9000 Ethernet Peripheral is <BR>
wired on the CMB (Cyclone Mother Board) 1.0.</em> <br>";
                        font = "small";
                     }
                  }
                  DATA 
                  {
                     $SPW/PORT address/width = "2";
                     $SPW/PORT data/width = "16";
                     $SBI/Data_Width = "16";
                     $SBI/Address_Width = "2";
                     $CONSTANTS/CONSTANT isp1161a1_REGISTERS_OFFSET/value = "0x0000";
                     $CONSTANTS/CONSTANT isp1161a1_DATA_BUS_WIDTH/value = "16";
                  }
               }
            }
         }
      }
      ASSOCIATED_FILES 
      {
         Add_Program = "default"; # No generator program, because this is a system-external component:
         Generator_Program = "--none--";
         Edit_Program = "default";
      }
      MODULE_DEFAULTS 
      {
         class = "mtx_avalon_isp1161a1";
         class_version = "1.0";
         WIZARD_SCRIPT_ARGUMENTS 
         {
            Is_Ethernet_Mac = "1";
            CONSTANTS 
            {
               CONSTANT isp1161a1_REGISTERS_OFFSET
               {
                  value = "0x0000";
                  comment = "(offset 0 or 0x300, depending on address bus wiring)";
               }
               CONSTANT isp1161a1_DATA_BUS_WIDTH
               {
                  value = "16";
                  comment = "(width 16 or 32, depending on data bus wiring)";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Instantiate_In_System_Module = "0";
            Wire_Test_Bench_Values = "1";
            Is_Enabled = "1";
         }
         SLAVE s1
         {
            SYSTEM_BUILDER_INFO 
            {
               Instantiate_In_System_Module = "0";
               Is_Enabled = "1";
               Is_Bus_Master = "0";
               Bus_Type = "avalon_tristate";
               Uses_Tri_State_Data_Bus = "1";
               Address_Alignment = "native";
               Address_Width = "2";
               Data_Width = "16";
               Has_IRQ = "1";
               Read_Wait_States = "30.0ns";
               Write_Wait_States = "30.0ns";
               Setup_Time = "30.0ns";
               Hold_Time = "10.0ns";
               Is_Memory_Device = "0";
               Date_Modified = "2004.09.24.10:51:51";
               IRQ_Number = "--unknown--";
               Base_Address = "--unknown--";
               Tri_State_Data_Bus = "--unknown--";
            }
            PORT_WIRING 
            {
               PORT irq
               {
                  direction = "output";
                  width = "1";
                  type = "irq";
                  test_bench_value = "0";
               }
               PORT address
               {
                  is_shared = "1";
                  direction = "input";
                  width = "2";
                  type = "address";
               }
               PORT data
               {
                  is_shared = "1";
                  direction = "inout";
                  width = "16";
                  type = "data";
               }
               PORT cs_n
               {
                  direction = "input";
                  width = "1";
                  type = "chipselect_n";
               }
               PORT iow_n
               {
                  is_shared = "1";
                  direction = "input";
                  width = "1";
                  type = "write_n";
               }
               PORT ior_n
               {
                  is_shared = "1";
                  direction = "input";
                  width = "1";
                  type = "read_n";
               }
               PORT reset
               {
                  direction = "input";
                  width = "1";
                  type = "reset";
               }
	       # this disables previous example design ports having reset_n port
               PORT reset_n
               {
                  direction = "input";
                  width = "1";
                  type = "reset_n";
                  Is_Enabled = "0";
               }
	       PORT ardy
               {
                  direction = "output";
                  width     = "1";
                  type      = "inhibitrequest_n";
                  Is_Enabled = "0";
               }
            }
         }
      }
   }