sanjiao_rom.fit.rpt

来自「在quartus软件下用VHDL语言实现DDS」· RPT 代码 · 共 602 行 · 第 1/5 页

; 1.5 V               ; 10 pF ; Not Available                      ;
; SSTL-3 Class I      ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-3 Class II     ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class I      ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class II     ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential SSTL-2 ; 30 pF ; (See SSTL-2)                       ;
; 3.3-V PCI           ; 10 pF ; 25 Ohm (Parallel)                  ;
; LVDS                ; 4 pF  ; 100 Ohm (Differential)             ;
; RSDS                ; 0 pF  ; 100 Ohm (Differential)             ;
+---------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                       ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------------+
; Compilation Hierarchy Node            ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                        ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------------+
; |sanjiao_rom                          ; 0 (0)       ; 0            ; 40960       ; 23   ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |sanjiao_rom                                                               ;
;    |altsyncram:altsyncram_component|  ; 0 (0)       ; 0            ; 40960       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |sanjiao_rom|altsyncram:altsyncram_component                               ;
;       |altsyncram_2ns:auto_generated| ; 0 (0)       ; 0            ; 40960       ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |sanjiao_rom|altsyncram:altsyncram_component|altsyncram_2ns:auto_generated ;
+---------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------+
; Delay Chain Summary                                                                  ;
+-------------+----------+---------------+---------------+-----------------------+-----+
; Name        ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+-------------+----------+---------------+---------------+-----------------------+-----+
; clock       ; Input    ; OFF           ; OFF           ; --                    ; --  ;
; address[0]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[1]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[2]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[3]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[4]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[5]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[6]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[7]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[8]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[9]  ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[10] ; Input    ; ON            ; ON            ; --                    ; --  ;
; address[11] ; Input    ; ON            ; ON            ; --                    ; --  ;
; q[0]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[1]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[2]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[3]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[4]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[5]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[6]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[7]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[8]        ; Output   ; --            ; --            ; --                    ; --  ;
; q[9]        ; Output   ; --            ; --            ; --                    ; --  ;
+-------------+----------+---------------+---------------+-----------------------+-----+


+-----------------------------------------------------------------------------------------------------------------+
; Pad To Core Delay Chain Fanout                                                                                  ;
+-----------------------------------------------------------------------------------+-------------------+---------+
; Source Pin / Fanout                                                               ; Pad To Core Index ; Setting ;
+-----------------------------------------------------------------------------------+-------------------+---------+
; clock                                                                             ;                   ;         ;
; address[0]                                                                        ;                   ;         ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a2 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a3 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a4 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a5 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a6 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a7 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a8 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a9 ; 1                 ; ON      ;
; address[1]                                                                        ;                   ;         ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a2 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a3 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a4 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a5 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a6 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a7 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a8 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a9 ; 0                 ; ON      ;
; address[2]                                                                        ;                   ;         ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a2 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a3 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a4 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a5 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a6 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a7 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a8 ; 0                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a9 ; 0                 ; ON      ;
; address[3]                                                                        ;                   ;         ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a2 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a3 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a4 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a5 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a6 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a7 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a8 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a9 ; 1                 ; ON      ;
; address[4]                                                                        ;                   ;         ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a0 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a1 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a2 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a3 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a4 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a5 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a6 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a7 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a8 ; 1                 ; ON      ;
;      - altsyncram:altsyncram_component|altsyncram_2ns:auto_generated|ram_block1a9 ; 1                 ; ON      ;
; address[5]                                                                        ;                   ;