choose.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 17 行

library ieee;
use ieee.std_logic_1164.all;

entity choose is
port(
input:in std_logic_vector(11 downto 0);
output:out std_logic
    );
end choose;

architecture behavior of choose is
begin
   process(input)
      begin
output<=input(11);
  end process;
end behavior;