leijia.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity leijia is 
port ( k:in std_logic_vector(3 downto 0);
       en:in std_logic;
       clk:in std_logic;
       sum:out std_logic_vector(11 downto 0)
     );
end leijia;

architecture behavior of leijia is
signal temp:std_logic_vector(11 downto 0);
begin 
  process(clk,en)
    begin 
      if(en='0')then
        temp<="000000000000";
      elsif(clk'event and clk='1')then
         temp<=temp+k;
      end if;
      sum<=temp;
    end process;
end behavior;