mux4_1.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;

entity mux4_1 is
port(  sine,sanjiao,juchi,juxing:in std_logic_vector(9 downto 0);
       a,b:in std_logic;
       cout:out std_logic_vector(9 downto 0)
);
end mux4_1;

architecture behavior of mux4_1 is
signal addr:std_logic_vector(1 downto 0);
begin
  process(a,b)
    begin
      addr(0)<=a;
      addr(1)<=b;
    case addr is
      when "00" => cout<=sine;
      when "01" => cout<=sanjiao;
      when "10" => cout<=juchi;
      when others => cout<=juxing;
    end case;
   end process;
end behavior;