mux8_1.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;

entity mux8_1 is
  port(dis_ljone,dis_ljten,dis_phone,dis_phten:in std_logic_vector(3 downto 0);
       f0,f1,f2,f3:in std_logic_vector(3 downto 0);
       res0,res1,res2,res3:out std_logic;
       a,b,c:in std_logic
       );
end mux8_1;

architecture behavior of mux8_1 is
signal addr:std_logic_vector(2 downto 0);
signal res:std_logic_vector(3 downto 0);
begin
process(a,b,c,addr) 
begin
addr(2)<=c;
addr(1)<=b;
addr(0)<=a;
  case addr is
    when"000"=> res<=dis_ljone;
    when"001"=> res<=dis_ljten;
    when"010"=> res<=dis_phone;
    when"011"=> res<=dis_phten;
    when"100"=> res<=f0;
    when"101"=> res<=f1;
    when"110"=> res<=f2;
    when"111"=> res<=f3;
    when others => null;
  end case;
end process;
res0<=res(0);
res1<=res(1);
res2<=res(2);
res3<=res(3);
end behavior;