juxing_rom.map.summary

来自「在quartus软件下用VHDL语言实现DDS」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Wed Apr 02 09:39:01 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : juxing_rom
Top-level Entity Name : juxing_rom
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 0
Total pins : 23
Total virtual pins : 0
Total memory bits : 40,960
Total PLLs : 0