📄 异步fifo及verilog原码_2.mht

📁 详细说明异步fifo的设计格雷码在地址的编码中的作用
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<P><STRONG>=D2=EC=B2=BDFIFO=BC=B0verilog=D4=AD=C2=EB_=D0=F8</STRONG> =
<BR><BR>=C1=BD=C6=AA=CE=C4=D5=C2=B5=C4=D4=AD=C2=EB=20
<BR><BR>//----------------------STYLE #1--------------------------=20
<BR><BR>module fifo1(rdata, wfull, rempty, wdata, winc, wclk, =
wrst_n,rinc, rclk,=20
rrst_n); <BR>parameter DSIZE =3D 8; <BR>parameter ASIZE =3D 4; =
<BR><BR>output=20
[DSIZE-1:0] rdata; <BR>output wfull; <BR>output rempty; <BR>input =
[DSIZE-1:0]=20
wdata; <BR>input winc, wclk, wrst_n; <BR>input rinc, rclk, rrst_n; =
<BR><BR>reg=20
wfull,rempty; <BR>reg [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr,=20
wq1_rptr,rq1_wptr; <BR>reg [ASIZE:0] rbin, wbin; <BR>reg [DSIZE-1:0]=20
mem[0:(1&lt;&lt;ASIZE)-1]; <BR>wire [ASIZE-1:0] waddr, raddr; <BR>wire =
[ASIZE:0]=20
rgraynext, rbinnext,wgraynext,wbinnext; <BR>wire rempty_val,wfull_val;=20
<BR>//-----------------=CB=AB=BF=DARAM=B4=E6=B4=A2=C6=F7-----------------=
--- <BR>assign rdata=3Dmem[raddr];=20
<BR>always@(posedge wclk) <BR>if (winc &amp;&amp; !wfull) mem[waddr] =
&lt;=3D=20
wdata; <BR>//-------------=CD=AC=B2=BDrptr =
=D6=B8=D5=EB------------------------- <BR>always=20
@(posedge wclk or negedge wrst_n) <BR>if (!wrst_n) {wq2_rptr,wq1_rptr} =
&lt;=3D 0;=20
<BR>else {wq2_rptr,wq1_rptr} &lt;=3D {wq1_rptr,rptr};=20
<BR>//-------------=CD=AC=B2=BDwptr=D6=B8=D5=EB--------------------------=
- <BR>always @(posedge rclk=20
or negedge rrst_n) <BR>if (!rrst_n) {rq2_wptr,rq1_wptr} &lt;=3D 0; =
<BR>else=20
{rq2_wptr,rq1_wptr} &lt;=3D {rq1_wptr,wptr};=20
<BR>//-------------rempty=B2=FA=C9=FA=D3=EBraddr=B2=FA=C9=FA-------------=
------ <BR>//-------------------=20
<BR>// GRAYSTYLE2 pointer <BR>//------------------- <BR>always @(posedge =
rclk or=20
negedge rrst_n) <BR>begin <BR>if (!rrst_n) {rbin, rptr} &lt;=3D 0; =
<BR>else {rbin,=20
rptr} &lt;=3D {rbinnext, rgraynext}; <BR>end <BR>// Memory read-address =
pointer=20
(okay to use binary to address memory) <BR>assign raddr =3D =
rbin[ASIZE-1:0];=20
<BR>assign rbinnext =3D rbin + (rinc &amp; ~rempty); <BR>assign =
rgraynext =3D=20
(rbinnext&gt;&gt;1) ^ rbinnext;=20
<BR>//--------------------------------------------------------------- =
<BR>//=20
FIFO empty when the next rptr =3D=3D synchronized wptr or on reset=20
<BR>//--------------------------------------------------------------- =
<BR>assign=20
rempty_val =3D (rgraynext =3D=3D rq2_wptr); <BR>always @(posedge rclk or =
negedge=20
rrst_n) <BR>begin <BR>if (!rrst_n) rempty &lt;=3D 1'b1; <BR>else rempty =
&lt;=3D=20
rempty_val; <BR>end=20
<BR>//---------------wfull=B2=FA=C9=FA=D3=EBwaddr=B2=FA=C9=FA------------=
------------------ <BR>//=20
GRAYSTYLE2 pointer <BR><BR>always @(posedge wclk or negedge wrst_n) =
<BR>if=20
(!wrst_n) {wbin, wptr} &lt;=3D 0; <BR>else {wbin, wptr} &lt;=3D =
{wbinnext,=20
wgraynext}; <BR><BR>// Memory write-address pointer (okay to use binary =
to=20
address memory) <BR>assign waddr =3D wbin[ASIZE-1:0]; <BR>assign =
wbinnext =3D wbin +=20
(winc &amp; ~wfull); <BR>assign wgraynext =3D (wbinnext&gt;&gt;1) ^ =
wbinnext;=20
<BR>//------------------------------------------------------------------ =
<BR>//=20
Simplified version of the three necessary full-tests: <BR>// assign=20
wfull_val=3D((wgnext[ADDRSIZE] !=3Dwq2_rptr[ADDRSIZE] ) &amp;&amp; =
<BR>//=20
(wgnext[ADDRSIZE-1] !=3Dwq2_rptr[ADDRSIZE-1]) &amp;&amp; <BR>//=20
(wgnext[ADDRSIZE-2:0]=3D=3Dwq2_rptr[ADDRSIZE-2:0]));=20
<BR>//------------------------------------------------------------------ =

<BR>assign wfull_val =3D (wgraynext=3D=3D{~wq2_rptr[ASIZE:ASIZE-1],=20
<BR>wq2_rptr[ASIZE-2:0]}); <BR><BR>always @(posedge wclk or negedge =
wrst_n)=20
<BR>if (!wrst_n) wfull &lt;=3D 1'b0; <BR>else wfull &lt;=3D wfull_val; =
<BR>endmodule=20
<BR><BR>//---------------------STYLE #2------------------------- =
<BR><BR>module=20
fifo2 (rdata, wfull, rempty, wdata, <BR>winc, wclk, wrst_n, rinc, rclk, =
rrst_n);=20
<BR>parameter DSIZE =3D 8; <BR>parameter ASIZE =3D 4; <BR>output =
[DSIZE-1:0] rdata;=20
<BR>output wfull; <BR>output rempty; <BR>input [DSIZE-1:0] wdata; =
<BR>input=20
winc, wclk, wrst_n; <BR>input rinc, rclk, rrst_n; <BR>wire [ASIZE-1:0] =
wptr,=20
rptr; <BR>wire [ASIZE-1:0] waddr, raddr; <BR><BR>async_cmp #(ASIZE)=20
async_cmp(.aempty_n(aempty_n), <BR>.afull_n(afull_n), <BR>.wptr(wptr),=20
.rptr(rptr), <BR>.wrst_n(wrst_n)); <BR><BR>fifomem2 #(DSIZE, ASIZE)=20
fifomem2(.rdata(rdata), <BR>.wdata(wdata), <BR>.waddr(wptr), =
<BR>.raddr(rptr),=20
<BR>.wclken(winc), <BR>.wclk(wclk)); <BR><BR>rptr_empty2 #(ASIZE)=20
rptr_empty2(.rempty(rempty), <BR>.rptr(rptr), <BR>.aempty_n(aempty_n),=20
<BR>.rinc(rinc), <BR>.rclk(rclk), <BR>.rrst_n(rrst_n)); =
<BR><BR>wptr_full2=20
#(ASIZE) wptr_full2(.wfull(wfull), <BR>.wptr(wptr), =
<BR>.afull_n(afull_n),=20
<BR>.winc(winc), <BR>.wclk(wclk), <BR>.wrst_n(wrst_n)); <BR>endmodule=20
<BR><BR>module fifomem2 (rdata, wdata, waddr, raddr, wclken, wclk);=20
<BR>parameter DATASIZE =3D 8; // Memory data word width <BR>parameter =
ADDRSIZE =3D=20
4; // Number of memory address bits <BR>parameter DEPTH =3D =
1&lt;&lt;ADDRSIZE; //=20
DEPTH =3D 2**ADDRSIZE <BR>output [DATASIZE-1:0] rdata; <BR>input =
[DATASIZE-1:0]=20
wdata; <BR>input [ADDRSIZE-1:0] waddr, raddr; <BR>input wclken, wclk; =
<BR>`ifdef=20
VENDORRAM <BR>// instantiation of a vendor's dual-port RAM =
<BR>VENDOR_RAM MEM=20
(.dout(rdata), .din(wdata), <BR>.waddr(waddr), .raddr(raddr),=20
<BR>.wclken(wclken), .clk(wclk)); <BR>`else <BR>reg [DATASIZE-1:0] MEM=20
[0:DEPTH-1]; <BR>assign rdata =3D MEM[raddr]; <BR>always @(posedge wclk) =
<BR>if=20
(wclken) MEM[waddr] &lt;=3D wdata; <BR>`endif <BR>endmodule =
<BR><BR>module=20
async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n); <BR>parameter =
ADDRSIZE =3D 4;=20
<BR>parameter N =3D ADDRSIZE-1; <BR>output aempty_n, afull_n; <BR>input =
[N:0]=20
wptr, rptr; <BR>input wrst_n; <BR>reg direction; <BR>wire high =3D 1'b1; =
<BR>wire=20
dirset_n =3D ~( (wptr[N]^rptr[N-1]) &amp; ~(wptr[N-1]^rptr[N])); =
<BR>wire dirclr_n=20
=3D ~((~(wptr[N]^rptr[N-1]) &amp; (wptr[N-1]^rptr[N])) | <BR>~wrst_n); =
<BR>always=20
@(posedge high or negedge dirset_n or negedge dirclr_n) <BR>if =
(!dirclr_n)=20
direction &lt;=3D 1'b0; <BR>else if (!dirset_n) direction &lt;=3D 1'b1; =
<BR>else=20
direction &lt;=3D high; <BR>//always @(negedge dirset_n or negedge =
dirclr_n)=20
<BR>//if (!dirclr_n) direction &lt;=3D 1'b0; <BR>//else direction =
&lt;=3D 1'b1;=20
<BR>assign aempty_n =3D ~((wptr =3D=3D rptr) &amp;&amp; !direction); =
<BR>assign=20
afull_n =3D ~((wptr =3D=3D rptr) &amp;&amp; direction); <BR>endmodule =
<BR><BR>module=20
rptr_empty2 (rempty, rptr, aempty_n, rinc, rclk, rrst_n); <BR>parameter =
ADDRSIZE=20
=3D 4; <BR>output rempty; <BR>output [ADDRSIZE-1:0] rptr; <BR>input =
aempty_n;=20
<BR>input rinc, rclk, rrst_n; <BR>reg [ADDRSIZE-1:0] rptr, rbin; <BR>reg =
rempty,=20
rempty2; <BR>wire [ADDRSIZE-1:0] rgnext, rbnext;=20
<BR>//--------------------------------------------------------------- =
<BR>//=20
GRAYSTYLE2 pointer=20
<BR>//--------------------------------------------------------------- =
<BR>always=20
@(posedge rclk or negedge rrst_n) <BR>if (!rrst_n) begin <BR>rbin =
&lt;=3D 0;=20
<BR>rptr &lt;=3D 0; <BR>end <BR>else begin <BR>rbin &lt;=3D rbnext; =
<BR>rptr &lt;=3D=20
rgnext; <BR>end=20
<BR>//--------------------------------------------------------------- =
<BR>//=20
increment the binary count if not empty=20
<BR>//--------------------------------------------------------------- =
<BR>assign=20
rbnext =3D !rempty ? rbin + rinc : rbin; <BR>assign rgnext =3D =
(rbnext&gt;&gt;1) ^=20
rbnext; // binary-to-gray conversion <BR>always @(posedge rclk or =
negedge=20
aempty_n) <BR>if (!aempty_n) {rempty,rempty2} &lt;=3D 2'b11; <BR>else=20
{rempty,rempty2} &lt;=3D {rempty2,~aempty_n}; <BR>endmodule =
<BR><BR>module=20
wptr_full2 (wfull, wptr, afull_n, winc, wclk, wrst_n); <BR>parameter =
ADDRSIZE =3D=20
4; <BR>output wfull; <BR>output [ADDRSIZE-1:0] wptr; <BR>input afull_n;=20
<BR>input winc, wclk, wrst_n; <BR>reg [ADDRSIZE-1:0] wptr, wbin; <BR>reg =
wfull,=20
wfull2; <BR>wire [ADDRSIZE-1:0] wgnext, wbnext;=20
<BR>//--------------------------------------------------------------- =
<BR>//=20
GRAYSTYLE2 pointer=20
<BR>//--------------------------------------------------------------- =
<BR>always=20
@(posedge wclk or negedge wrst_n) <BR>if (!wrst_n) begin <BR>wbin =
&lt;=3D 0;=20
<BR>wptr &lt;=3D 0; <BR>end <BR>else begin <BR>wbin &lt;=3D wbnext; =
<BR>wptr &lt;=3D=20
wgnext; <BR>end=20
<BR>//--------------------------------------------------------------- =
<BR>//=20
increment the binary count if not full=20
<BR>//--------------------------------------------------------------- =
<BR>assign=20
wbnext =3D !wfull ? wbin + winc : wbin; <BR>assign wgnext =3D =
(wbnext&gt;&gt;1) ^=20
wbnext; // binary-to-gray conversion <BR>always @(posedge wclk or =
negedge wrst_n=20
or negedge afull_n) <BR>if (!wrst_n ) {wfull,wfull2} &lt;=3D 2'b00; =
<BR>else if=20
(!afull_n) {wfull,wfull2} &lt;=3D 2'b11; <BR>else {wfull,wfull2} &lt;=3D =

{wfull2,~afull_n}; <BR>endmodule=20
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