ddr2_normal_mode_read_write_example.c

TI dm643 DDR 配置源代码,可以直接下载到板子上运行

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *  ============================================================================
 */

/** ============================================================================
 *
 *   @file  Ddr2_normal_mode_read_write_example.c
 *
 *   @path $(CSLPATH)\example\dm648\ddr2\src
 *
 *   @desc  Read write example of DDR2 in Normal Mode
 *
 *  ============================================================================
 *   @n Target Platform: EVM
 *  ============================================================================
 *   @n <b> Example Description </b>
 *   @n This example, 
 *        1. Enables the DDR2 module
 *        2 Sets up the hardware to default values and Normal Mode.
 *        3 Writes the Invalid values into DDR2 SDRAM area to over write the 
 *           previous values.
 *        4 Writes valid data
 *        5 Does the data comparision to ensure the written data is proper or 
 *           not and 
 *        6 Displays the messages based on step 5
 *
 * =============================================================================
 *      
 *   <b> Procedure to run the example </b>
 *   @verbatim
 *      1. Configure the CCS setup to work with the emulator being used
 *      2. Please refer CCS manual for setup configuration and loading 
 *         proper GEL file
 *      3. Launch CCS window
 *      4. Open project Ddr2_normal_mode_read_write_example.pjt
 *      5. Build the project and load the .out file of the project.
 *          
 *   @endverbatim
 *
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  21-May-2005 RM  File created
 *  30-Nov-2005 NG  Updated documentation
 *  06-Feb-2006 ds  Changed to use DEV functional layer 
 *  21-May-2007 NS  File modified.
 * =============================================================================
 */
#include <cslr_ddr2.h>
#include <cslr_sys.h>
#include <stdio.h>
#include <soc.h> 
#include <cslr_psc.h>

/** Result - Passed */
#define DATA_MATCH_SUCCESS    1
/** Result - Failed */
#define DATA_MATCH_FAIL       0

/** Data count(number write/readbacks) */
#define DATA_CNT    10

#define EMIFB_CE0_BASE_ADDR            (0xE0000000u)
#define SDRAM_REFRESH_RATE_DEFAULT     (0x00000753u)

/* Forwards declarations */
void ddr2ReadWrite(void);
void enableDdr2 (void);

/*
 * =============================================================================
 *   @func   main
 *
 *   @desc
 *     This is the main routine for the file.  
 *    
 * =============================================================================
 */
void main (
    void
)
{   
    /* Enable the ddr2 */
    enableDdr2 ();

    /* read_write functionality of DDR2 */
    ddr2ReadWrite();   
    return; 
}

/*
 * =============================================================================
 *   @func   ddr2ReadWrite
 *
 *   @desc
 *       example code showing how to use CSL macros, setting up DDR2 
 *
 * =============================================================================
 */
void ddr2ReadWrite (
    void
)
{
    volatile Uint32     result, index ;
    Uint32              tempData; 
    Uint32              mask;

    /* Pointer that points to SDRAM start area */
    Uint32 *pDdr2Data = (Uint32 *)EMIFB_CE0_BASE_ADDR ;
    
    /* Pointer to register overlay structure for DDR2 */    
    CSL_Ddr2RegsOvly ddr2Regs = (CSL_Ddr2RegsOvly)CSL_DDR2_0_REGS;         

    /* Refresh rate*/     
    CSL_FINS(ddr2Regs->SDRFC, DDR2_SDRFC_REFRESH_RATE, SDRAM_REFRESH_RATE_DEFAULT);  

    /* Writing the ddr2 sdram Settings in SDRAM Config register */  
    mask = ~( 
              (CSL_DDR2_SDCFG_TIMUNLOCK_MASK) |
              (CSL_DDR2_SDCFG_CL_MASK) | 
              (CSL_DDR2_SDCFG_IBANK_MASK) |
              (CSL_DDR2_SDCFG_PAGESIZE_MASK)|
              (CSL_DDR2_SDCFG_NM_MASK));   
               
    /* Set the TIMUNLOCK bit : A write to this bit will cause the DDR2 Memory 
                               Controller to start the SDRAM initialization sequence. */   
    /* Set the CAS latency of 5 */        
    /* Set the Internal SDRAM bank to 4 */       
    /* Set the DDR2 data bus width to 32 bit */   
    /* Set the page size to 256-word page */     
        
    ddr2Regs->SDCFG = (ddr2Regs->SDCFG & mask ) |
                          (CSL_FMK(DDR2_SDCFG_TIMUNLOCK, 
                                   CSL_DDR2_SDCFG_TIMUNLOCK_SET)) |
                          (CSL_FMKT(DDR2_SDCFG_CL, FIVE)) |
                          (CSL_FMKT(DDR2_SDCFG_IBANK, FOUR)) |
                          (CSL_FMKT(DDR2_SDCFG_NM, 32BIT )) |
                          (CSL_FMKT(DDR2_SDCFG_PAGESIZE, 256W_PAGE ));  
                          
    /* Unlock the BOOT_UNLOCK bit */                                          
    CSL_FINS(ddr2Regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, \
                                      CSL_DDR2_SDCFG_BOOT_UNLOCK_UNLOCKED);
    /* Set the DDR2 SDRAM drive strength to Normal */                                  
    CSL_FINS(ddr2Regs->SDCFG, DDR2_SDCFG_DDR_DRIVE, \
                                      CSL_DDR2_SDCFG_DDR_DRIVE_NORMAL);
    /* Lock the BOOT_UNLOCK bit */                                  
    CSL_FINS(ddr2Regs->SDCFG, DDR2_SDCFG_BOOT_UNLOCK, \
                                      CSL_DDR2_SDCFG_BOOT_UNLOCK_LOCKED); 
                                            
   /* Locking the timing_unlock to prevent further changes */
    CSL_FINS(ddr2Regs->SDCFG, DDR2_SDCFG_TIMUNLOCK, 
                                      CSL_DDR2_SDCFG_TIMUNLOCK_CLEAR);                                           
 
    
   /* Write 'invalid' values into DDR2 SDRAM area. This is to overwrite the 
    * previous valid values
    */
    tempData = 0xdeadbeef;
    for (index = 0; index < DATA_CNT; index++) {
        pDdr2Data[index] =  tempData;
    }

    /* Write **valid** values into SDRAM area. */
    tempData = 0x56780000;
    for (index = 0; index < DATA_CNT; index++) {
        pDdr2Data[index] = tempData + index ;
    }

    /* Verify that the data was indeed written */
    result = DATA_MATCH_SUCCESS;
    for (index = 0; index < DATA_CNT; index++) {
        if (pDdr2Data[index] != (tempData + index)) {
            result = DATA_MATCH_FAIL;                     
            break ;
        }
    }

   /* Print the appropriate message based on result */
    if (result == DATA_MATCH_SUCCESS) {     
        printf("\nWrite to and Read from DDR2 SDRAM is Successful\n"); 
    }
    else {      
        printf("\nWrite to and Read from DDR2 SDRAM is NOT Successful\n"); 
    }   
}

/*
 * ============================================================================
 *   @func   enableDdr2
 *
 *   @desc
 *     This function enables the powerSaver for DDR2 module
 *
 *  @arg  
 *      None
 *
 *  @return
 *      None
 * ============================================================================
*/
void enableDdr2 (void)
{

    /* Pointer to register overlay structure for PSC */
    CSL_PscRegsOvly pscRegs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;
    
    /* enable DDR2 LPSC*/
    pscRegs->MDCTL[CSL_PSC_EMIF3D] = CSL_FMKT(PSC_MDCTL_NEXT, ENABLE) | 
                                   CSL_FMKT(PSC_MDCTL_LRST, DEASSERT);
    
    pscRegs->PTCMD = CSL_FMKT(PSC_PTCMD_GO0, SET);
    
    while (CSL_FEXT(pscRegs->MDSTAT[CSL_PSC_EMIF3D], PSC_MDSTAT_STATE)
          != CSL_PSC_MDSTAT_STATE_ENABLE);
}