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📄 c8051f120.lst

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 180          
 181          /*  CPT0CN  0x88 */
 182          
 183          sbit CP0EN   = CPT0CN ^ 7;          /* COMPARATOR 0 ENABLE                 */
 184          sbit CP0OUT  = CPT0CN ^ 6;          /* COMPARATOR 0 OUTPUT                 */
 185          sbit CP0RIF  = CPT0CN ^ 5;          /* COMPARATOR 0 RISING EDGE INTERRUPT  */
 186          sbit CP0FIF  = CPT0CN ^ 4;          /* COMPARATOR 0 FALLING EDGE INTERRUPT */
 187          sbit CP0HYP1 = CPT0CN ^ 3;          /* COMPARATOR 0 POSITIVE HYSTERESIS 1  */
 188          sbit CP0HYP0 = CPT0CN ^ 2;          /* COMPARATOR 0 POSITIVE HYSTERESIS 0  */
 189          sbit CP0HYN1 = CPT0CN ^ 1;          /* COMPARATOR 0 NEGATIVE HYSTERESIS 1  */
 190          sbit CP0HYN0 = CPT0CN ^ 0;          /* COMPARATOR 0 NEGATIVE HYSTERESIS 0  */
 191          
 192          /*  CPT1CN  0x88 */
 193          sbit CP1EN   = CPT1CN ^ 7;          /* COMPARATOR 1 ENABLE                 */
 194          sbit CP1OUT  = CPT1CN ^ 6;          /* COMPARATOR 1 OUTPUT                 */
 195          sbit CP1RIF  = CPT1CN ^ 5;          /* COMPARATOR 1 RISING EDGE INTERRUPT  */
 196          sbit CP1FIF  = CPT1CN ^ 4;          /* COMPARATOR 1 FALLING EDGE INTERRUPT */
 197          sbit CP1HYP1 = CPT1CN ^ 3;          /* COMPARATOR 1 POSITIVE HYSTERESIS 1  */
 198          sbit CP1HYP0 = CPT1CN ^ 2;          /* COMPARATOR 1 POSITIVE HYSTERESIS 0  */
 199          sbit CP1HYN1 = CPT1CN ^ 1;          /* COMPARATOR 1 NEGATIVE HYSTERESIS 1  */
 200          sbit CP1HYN0 = CPT1CN ^ 0;          /* COMPARATOR 1 NEGATIVE HYSTERESIS 0  */
 201          
 202          /*  FLSTAT  0x88 */
 203          sbit FLBUSY = FLSTAT ^ 0;           /* FLASH BUSY */
 204          
 205          /*  SCON0  0x98 */
 206          sbit SM00 = SCON0 ^ 7;              /* UART 0 MODE 0            */
 207          sbit SM10 = SCON0 ^ 6;              /* UART 0 MODE 1            */
 208          sbit SM20 = SCON0 ^ 5;              /* UART 0 MULTIPROCESSOR EN */
 209          sbit REN0 = SCON0 ^ 4;              /* UART 0 RX ENABLE         */
 210          sbit TB80 = SCON0 ^ 3;              /* UART 0 TX BIT 8          */
 211          sbit RB80 = SCON0 ^ 2;              /* UART 0 RX BIT 8          */
 212          sbit TI0  = SCON0 ^ 1;              /* UART 0 TX INTERRUPT FLAG */
 213          sbit RI0  = SCON0 ^ 0;              /* UART 0 RX INTERRUPT FLAG */
 214          
 215          /*  SCON1  0x98 */
 216          sbit S1MODE = SCON1 ^ 7;            /* UART 1 MODE              */
 217          sbit MCE1   = SCON1 ^ 5;            /* UART 1 MCE               */
 218          sbit REN1   = SCON1 ^ 4;            /* UART 1 RX ENABLE         */
 219          sbit TB81   = SCON1 ^ 3;            /* UART 1 TX BIT 8          */
 220          sbit RB81   = SCON1 ^ 2;            /* UART 1 RX BIT 8          */
 221          sbit TI1    = SCON1 ^ 1;            /* UART 1 TX INTERRUPT FLAG */
 222          sbit RI1    = SCON1 ^ 0;            /* UART 1 RX INTERRUPT FLAG */
 223          
 224          /*  IE  0xA8 */
 225          sbit EA    = IE ^ 7;                /* GLOBAL INTERRUPT ENABLE      */
 226          sbit ET2   = IE ^ 5;                /* TIMER 2 INTERRUPT ENABLE     */
 227          sbit ES0   = IE ^ 4;                /* UART0 INTERRUPT ENABLE       */
 228          sbit ET1   = IE ^ 3;                /* TIMER 1 INTERRUPT ENABLE     */
 229          sbit EX1   = IE ^ 2;                /* EXTERNAL INTERRUPT 1 ENABLE  */
 230          sbit ET0   = IE ^ 1;                /* TIMER 0 INTERRUPT ENABLE     */
 231          sbit EX0   = IE ^ 0;                /* EXTERNAL INTERRUPT 0 ENABLE  */
 232          
 233          
 234          /*  IP  0xB8 */
 235          sbit PT2   = IP ^ 5;                /* TIMER 2 PRIORITY                 */
 236          sbit PS    = IP ^ 4;                /* SERIAL PORT PRIORITY             */
 237          sbit PT1   = IP ^ 3;                /* TIMER 1 PRIORITY                 */
 238          sbit PX1   = IP ^ 2;                /* EXTERNAL INTERRUPT 1 PRIORITY    */
 239          sbit PT0   = IP ^ 1;                /* TIMER 0 PRIORITY                 */
 240          sbit PX0   = IP ^ 0;                /* EXTERNAL INTERRUPT 0 PRIORITY    */
 241          
C51 COMPILER V8.02   C8051F120                                                             07/24/2008 14:18:51 PAGE 5   

 242          /* SMB0CN 0xC0 */
 243          sbit BUSY   = SMB0CN ^ 7;           /* SMBUS 0 BUSY                    */
 244          sbit ENSMB  = SMB0CN ^ 6;           /* SMBUS 0 ENABLE                  */
 245          sbit STA    = SMB0CN ^ 5;           /* SMBUS 0 START FLAG              */
 246          sbit STO    = SMB0CN ^ 4;           /* SMBUS 0 STOP FLAG               */
 247          sbit SI     = SMB0CN ^ 3;           /* SMBUS 0 INTERRUPT PENDING FLAG  */
 248          sbit AA     = SMB0CN ^ 2;           /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
 249          sbit SMBFTE = SMB0CN ^ 1;           /* SMBUS 0 FREE TIMER ENABLE       */
 250          sbit SMBTOE = SMB0CN ^ 0;           /* SMBUS 0 TIMEOUT ENABLE          */
 251          
 252          /*  TMR2CN  0xC8 */
 253          sbit TF2   = TMR2CN ^ 7;            /* TIMER 2 OVERFLOW FLAG        */
 254          sbit EXF2  = TMR2CN ^ 6;            /* TIMER 2 EXTERNAL FLAG        */
 255          sbit EXEN2 = TMR2CN ^ 3;            /* TIMER 2 EXTERNAL ENABLE FLAG */
 256          sbit TR2   = TMR2CN ^ 2;            /* TIMER 2 ON/OFF CONTROL       */
 257          sbit CT2   = TMR2CN ^ 1;            /* TIMER 2 COUNTER SELECT       */
 258          sbit CPRL2 = TMR2CN ^ 0;            /* TIMER 2 CAPTURE SELECT       */
 259          
 260          /*  TMR3CN  0xC8 */
 261          sbit TF3   = TMR3CN ^ 7;            /* TIMER 3 OVERFLOW FLAG        */
 262          sbit EXF3  = TMR3CN ^ 6;            /* TIMER 3 EXTERNAL FLAG        */
 263          sbit EXEN3 = TMR3CN ^ 3;            /* TIMER 3 EXTERNAL ENABLE FLAG */
 264          sbit TR3   = TMR3CN ^ 2;            /* TIMER 3 ON/OFF CONTROL       */
 265          sbit CT3   = TMR3CN ^ 1;            /* TIMER 3 COUNTER SELECT       */
 266          sbit CPRL3 = TMR3CN ^ 0;            /* TIMER 3 CAPTURE SELECT       */
 267          
 268          /*  TMR4CN  0xC8 */
 269          sbit TF4   = TMR4CN ^ 7;            /* TIMER 4 OVERFLOW FLAG        */
 270          sbit EXF4  = TMR4CN ^ 6;            /* TIMER 4 EXTERNAL FLAG        */
 271          sbit EXEN4 = TMR4CN ^ 3;            /* TIMER 4 EXTERNAL ENABLE FLAG */
 272          sbit TR4   = TMR4CN ^ 2;            /* TIMER 4 ON/OFF CONTROL       */
 273          sbit CT4   = TMR4CN ^ 1;            /* TIMER 4 COUNTER SELECT       */
 274          sbit CPRL4 = TMR4CN ^ 0;            /* TIMER 4 CAPTURE SELECT       */
 275          
 276          /*  PSW  */
 277          sbit CY  = PSW ^ 7;                 /* CARRY FLAG              */
 278          sbit AC  = PSW ^ 6;                 /* AUXILIARY CARRY FLAG    */
 279          sbit F0  = PSW ^ 5;                 /* USER FLAG 0             */
 280          sbit RS1 = PSW ^ 4;                 /* REGISTER BANK SELECT 1  */
 281          sbit RS0 = PSW ^ 3;                 /* REGISTER BANK SELECT 0  */
 282          sbit OV  = PSW ^ 2;                 /* OVERFLOW FLAG           */
 283          sbit F1  = PSW ^ 1;                 /* USER FLAG 1             */
 284          sbit P   = PSW ^ 0;                 /* ACCUMULATOR PARITY FLAG */
 285          
 286          /* PCA0CN D8H */
 287          sbit CF   = PCA0CN ^ 7;             /* PCA 0 COUNTER OVERFLOW FLAG   */
 288          sbit CR   = PCA0CN ^ 6;             /* PCA 0 COUNTER RUN CONTROL BIT */
 289          sbit CCF5 = PCA0CN ^ 5;             /* PCA 0 MODULE 5 INTERRUPT FLAG */
 290          sbit CCF4 = PCA0CN ^ 4;             /* PCA 0 MODULE 4 INTERRUPT FLAG */
 291          sbit CCF3 = PCA0CN ^ 3;             /* PCA 0 MODULE 3 INTERRUPT FLAG */
 292          sbit CCF2 = PCA0CN ^ 2;             /* PCA 0 MODULE 2 INTERRUPT FLAG */
 293          sbit CCF1 = PCA0CN ^ 1;             /* PCA 0 MODULE 1 INTERRUPT FLAG */
 294          sbit CCF0 = PCA0CN ^ 0;             /* PCA 0 MODULE 0 INTERRUPT FLAG */
 295          
 296          /* ADC0CN E8H */
 297          sbit AD0EN   = ADC0CN ^ 7;          /* ADC 0 ENABLE                   */
 298          sbit AD0TM   = ADC0CN ^ 6;          /* ADC 0 TRACK MODE               */
 299          sbit AD0INT  = ADC0CN ^ 5;          /* ADC 0 EOC INTERRUPT FLAG       */
 300          sbit AD0BUSY = ADC0CN ^ 4;          /* ADC 0 BUSY FLAG                */
 301          sbit AD0CM1  = ADC0CN ^ 3;          /* ADC 0 CONVERT START MODE BIT 1 */
 302          sbit AD0CM0  = ADC0CN ^ 2;          /* ADC 0 CONVERT START MODE BIT 0 */
 303          sbit AD0WINT = ADC0CN ^ 1;          /* ADC 0 WINDOW INTERRUPT FLAG    */
C51 COMPILER V8.02   C8051F120                                                             07/24/2008 14:18:51 PAGE 6   

 304          sbit AD0LJST = ADC0CN ^ 0;          /* ADC 0 RIGHT JUSTIFY DATA BIT   */
 305          
 306          /* ADC2CN E8H */
 307          sbit AD2EN   = ADC2CN ^ 7;          /* ADC 2 ENABLE                   */
 308          sbit AD2TM   = ADC2CN ^ 6;          /* ADC 2 TRACK MODE               */
 309          sbit AD2INT  = ADC2CN ^ 5;          /* ADC 2 EOC INTERRUPT FLAG       */
 310          sbit AD2BUSY = ADC2CN ^ 4;          /* ADC 2 BUSY FLAG                */
 311          sbit AD2CM2  = ADC2CN ^ 3;          /* ADC 2 CONVERT START MODE BIT 2 */
 312          sbit AD2CM1  = ADC2CN ^ 2;          /* ADC 2 CONVERT START MODE BIT 1 */
 313          sbit AD2CM0  = ADC2CN ^ 1;          /* ADC 2 CONVERT START MODE BIT 0 */
 314          sbit AD2WINT = ADC2CN ^ 0;          /* ADC 2 WINDOW INTERRUPT FLAG    */
 315          
 316          /* SPI0CN F8H */
 317          sbit SPIF   = SPI0CN ^ 7;           /* SPI 0 INTERRUPT FLAG       */
 318          sbit WCOL   = SPI0CN ^ 6;           /* SPI 0 WRITE COLLISION FLAG */
 319          sbit MODF   = SPI0CN ^ 5;           /* SPI 0 MODE FAULT FLAG      */
 320          sbit RXOVRN = SPI0CN ^ 4;           /* SPI 0 RX OVERRUN FLAG      */
 321          sbit NSSMD1 = SPI0CN ^ 3;           /* SPI 0 SLAVE SELECT MODE 1  */
 322          sbit NSSMD0 = SPI0CN ^ 2;           /* SPI 0 SLAVE SELECT MODE 0  */
 323          sbit TXBMT  = SPI0CN ^ 1;           /* SPI 0 TX BUFFER EMPTY FLAG */
 324          sbit SPIEN  = SPI0CN ^ 0;           /* SPI 0 SPI ENABLE           */
 325          
 326          
 327          
 328          /* SFR PAGE DEFINITIONS */
 329          #define  CONFIG_PAGE       0x0F     /* SYSTEM AND PORT CONFIGURATION PAGE */
 330          #define  LEGACY_PAGE       0x00     /* LEGACY SFR PAGE                    */
 331          #define  TIMER01_PAGE      0x00     /* TIMER 0 AND TIMER 1                */
 332          #define  CPT0_PAGE         0x01     /* COMPARATOR 0                       */
 333          #define  CPT1_PAGE         0x02     /* COMPARATOR 1                       */
 334          #define  UART0_PAGE        0x00     /* UART 0                             */
 335          #define  UART1_PAGE        0x01     /* UART 1                             */
 336          #define  SPI0_PAGE         0x00     /* SPI 0                              */
 337          #define  EMI0_PAGE         0x00     /* EXTERNAL MEMORY INTERFACE          */
 338          #define  ADC0_PAGE         0x00     /* ADC 0                              */
 339          #define  ADC2_PAGE         0x02     /* ADC 2                              */
 340          #define  SMB0_PAGE         0x00     /* SMBUS 0                            */
 341          #define  TMR2_PAGE         0x00     /* TIMER 2                            */
 342          #define  TMR3_PAGE         0x01     /* TIMER 3                            */
 343          #define  TMR4_PAGE         0x02     /* TIMER 4                            */
 344          #define  DAC0_PAGE         0x00     /* DAC 0                              */
 345          #define  DAC1_PAGE         0x01     /* DAC 1                              */
 346          #define  PCA0_PAGE         0x00     /* PCA 0                              */
 347          #define  REF0_PAGE         0x00     /**/
 348          #define  PLL0_PAGE         0x0F     /* PLL 0                              */
 349          
 350          
 351          #endif


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =   ----    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

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