📄 c8051f120.lst
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C51 COMPILER V8.02 C8051F120 07/24/2008 14:18:51 PAGE 1
C51 COMPILER V8.02, COMPILATION OF MODULE C8051F120
OBJECT MODULE PLACED IN c8051F120.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\c51.exe c8051F120.h DB OE BR
line level source
1 #ifndef C8051F120_H
2 #define C8051F120_H
3 /*---------------------------------------------------------------------------
4 ; Copyright (C) 2002 CYGNAL INTEGRATED PRODUCTS, INC.
5 ; All rights reserved.
6 ;
7 ;
8 ; FILE NAME : C8051F120.H
9 ; TARGET MCUs : C8051F120, 'F121, 'F122, 'F123, 'F124, 'F125, "F126, 'F127
10 ; DESCRIPTION : Register/bit definitions for the C8051F12x product family.
11 ;
12 ; REVISION 1.5
13 ;
14 ;---------------------------------------------------------------------------*/
15
16 /* BYTE Registers */
17 sfr P0 = 0x80; /* PORT 0 */
18 sfr SP = 0x81; /* STACK POINTER */
19 sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */
20 sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */
21 sfr SFRPAGE = 0x84; /* SFR PAGE SELECT */
22 sfr SFRNEXT = 0x85; /* SFR STACK NEXT PAGE */
23 sfr SFRLAST = 0x86; /* SFR STACK LAST PAGE */
24 sfr PCON = 0x87; /* POWER CONTROL */
25 sfr TCON = 0x88; /* TIMER CONTROL */
26 sfr CPT0CN = 0x88; /* COMPARATOR 0 CONTROL */
27 sfr CPT1CN = 0x88; /* COMPARATOR 1 CONTROL */
28 sfr FLSTAT = 0x88; /* FLASH STATUS */
29 sfr TMOD = 0x89; /* TIMER MODE */
30 sfr CPT0MD = 0x89; /* COMPARATOR 0 CONFIGURATION */
31 sfr CPT1MD = 0x89; /* COMPARATOR 1 CONFIGURATION */
32 sfr PLL0CN = 0x89; /* PLL 0 CONTROL */
33 sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */
34 sfr OSCICN = 0x8A; /* INTERNAL OSCILLATOR CONTROL */
35 sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */
36 sfr OSCICL = 0x8B; /* INTERNAL OSCILLATOR CALIBRATION */
37 sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */
38 sfr OSCXCN = 0x8C; /* EXTERNAL OSCILLATOR CONTROL */
39 sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */
40 sfr PLL0DIV = 0x8D; /* PLL 0 DIVIDER */
41 sfr CKCON = 0x8E; /* TIMER 0/1 CLOCK CONTROL */
42 sfr PLL0MUL = 0x8E; /* PLL 0 MULTIPLIER */
43 sfr PSCTL = 0x8F; /* FLASH WRITE/ERASE CONTROL */
44 sfr PLL0FLT = 0x8F; /* PLL 0 FILTER */
45 sfr P1 = 0x90; /* PORT 1 */
46 sfr SSTA0 = 0x91; /* UART 0 STATUS */
47 sfr SFRPGCN = 0x96; /* SFR PAGE CONTROL */
48 sfr CLKSEL = 0x97; /* SYSTEM CLOCK SELECT */
49 sfr SCON0 = 0x98; /* UART 0 CONTROL */
50 sfr SCON1 = 0x98; /* UART 1 CONTROL */
51 sfr SBUF0 = 0x99; /* UART 0 BUFFER */
52 sfr SBUF1 = 0x99; /* UART 1 BUFFER */
53 sfr SPI0CFG = 0x9A; /* SPI 0 CONFIGURATION */
54 sfr CCH0MA = 0x9A; /* CACHE MISS ACCUMULATOR */
55 sfr SPI0DAT = 0x9B; /* SPI 0 DATA */
C51 COMPILER V8.02 C8051F120 07/24/2008 14:18:51 PAGE 2
56 sfr P4MDOUT = 0x9C; /* PORT 4 OUTPUT MODE */
57 sfr SPI0CKR = 0x9D; /* SPI 0 CLOCK RATE CONTROL */
58 sfr P5MDOUT = 0x9D; /* PORT 5 OUTPUT MODE */
59 sfr P6MDOUT = 0x9E; /* PORT 6 OUTPUT MODE */
60 sfr P7MDOUT = 0x9F; /* PORT 7 OUTPUT MODE */
61 sfr P2 = 0xA0; /* PORT 2 */
62 sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */
63 sfr CCH0CN = 0xA1; /* CACHE CONTROL */
64 sfr EMI0CN = 0xA2; /* EMIF CONTROL */
65 sfr CCH0TN = 0xA2; /* CACHE TUNING REGISTER */
66 sfr EMI0CF = 0xA3; /* EMIF CONFIGURATION */
67 sfr CCH0LC = 0xA3; /* CACHE LOCK */
68 sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE */
69 sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE */
70 sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
71 sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
72 sfr IE = 0xA8; /* INTERRUPT ENABLE */
73 sfr SADDR0 = 0xA9; /* UART 0 SLAVE ADDRESS */
74 sfr P1MDIN = 0xAD; /* PORT 1 INPUT MODE */
75 sfr P3 = 0xB0; /* PORT 3 */
76 sfr PSBANK = 0xB1; /* FLASH BANK SELECT */
77 sfr FLSCL = 0xB7; /* FLASH SCALE */
78 sfr FLACL = 0xB7; /* FLASH ACCESS LIMIT */
79 sfr IP = 0xB8; /* INTERRUPT PRIORITY */
80 sfr SADEN0 = 0xB9; /* UART 0 SLAVE ADDRESS MASK */
81 sfr AMX0CF = 0xBA; /* ADC 0 MUX CONFIGURATION */
82 sfr AMX2CF = 0xBA; /* ADC 2 MUX CONFIGURATION */
83 sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL SELECTION */
84 sfr AMX2SL = 0xBB; /* ADC 2 MUX CHANNEL SELECTION */
85 sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
86 sfr ADC2CF = 0xBC; /* ADC 2 CONFIGURATION */
87 sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
88 sfr ADC2 = 0xBE; /* ADC 2 DATA */
89 sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
90 sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
91 sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
92 sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
93 sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
94 sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
95 sfr ADC2GT = 0xC4; /* ADC 2 GREATER-THAN REGISTER */
96 sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
97 sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
98 sfr ADC2LT = 0xC6; /* ADC 2 LESS-THAN REGISTER */
99 sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
100 sfr TMR2CN = 0xC8; /* TIMER 2 CONTROL */
101 sfr TMR3CN = 0xC8; /* TIMER 3 CONTROL */
102 sfr TMR4CN = 0xC8; /* TIMER 4 CONTROL */
103 sfr P4 = 0xC8; /* PORT 4 */
104 sfr TMR2CF = 0xC9; /* TIMER 2 CONFIGURATION */
105 sfr TMR3CF = 0xC9; /* TIMER 3 CONFIGURATION */
106 sfr TMR4CF = 0xC9; /* TIMER 4 CONFIGURATION */
107 sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
108 sfr RCAP3L = 0xCA; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
109 sfr RCAP4L = 0xCA; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
110 sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
111 sfr RCAP3H = 0xCB; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
112 sfr RCAP4H = 0xCB; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
113 sfr TMR2L = 0xCC; /* TIMER 2 - LOW BYTE */
114 sfr TMR3L = 0xCC; /* TIMER 3 - LOW BYTE */
115 sfr TMR4L = 0xCC; /* TIMER 4 - LOW BYTE */
116 sfr TMR2H = 0xCD; /* TIMER 2 - HIGH BYTE */
117 sfr TMR3H = 0xCD; /* TIMER 3 - HIGH BYTE */
C51 COMPILER V8.02 C8051F120 07/24/2008 14:18:51 PAGE 3
118 sfr TMR4H = 0xCD; /* TIMER 4 - HIGH BYTE */
119 sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK RATE */
120 sfr PSW = 0xD0; /* PROGRAM STATUS WORD */
121 sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0 CONTROL */
122 sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW BYTE */
123 sfr DAC1L = 0xD2; /* DAC 1 REGISTER - LOW BYTE */
124 sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH BYTE */
125 sfr DAC1H = 0xD3; /* DAC 1 REGISTER - HIGH BYTE */
126 sfr DAC0CN = 0xD4; /* DAC 0 CONTROL */
127 sfr DAC1CN = 0xD4; /* DAC 1 CONTROL */
128 sfr PCA0CN = 0xD8; /* PCA 0 COUNTER CONTROL */
129 sfr P5 = 0xD8; /* PORT 5 */
130 sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
131 sfr PCA0CPM0 = 0xDA; /* PCA 0 MODULE 0 CONTROL */
132 sfr PCA0CPM1 = 0xDB; /* PCA 0 MODULE 1 CONTROL */
133 sfr PCA0CPM2 = 0xDC; /* PCA 0 MODULE 2 CONTROL */
134 sfr PCA0CPM3 = 0xDD; /* PCA 0 MODULE 3 CONTROL */
135 sfr PCA0CPM4 = 0xDE; /* PCA 0 MODULE 4 CONTROL */
136 sfr PCA0CPM5 = 0xDF; /* PCA 0 MODULE 5 CONTROL */
137 sfr ACC = 0xE0; /* ACCUMULATOR */
138 sfr PCA0CPL5 = 0xE1; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
139 sfr XBR0 = 0xE1; /* CROSSBAR CONFIGURATION REGISTER 0 */
140 sfr PCA0CPH5 = 0xE2; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
141 sfr XBR1 = 0xE2; /* CROSSBAR CONFIGURATION REGISTER 1 */
142 sfr XBR2 = 0xE3; /* CROSSBAR CONFIGURATION REGISTER 2 */
143 sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
144 sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
145 sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
146 sfr ADC2CN = 0xE8; /* ADC 2 CONTROL */
147 sfr P6 = 0xE8; /* PORT 6 */
148 sfr PCA0CPL2 = 0xE9; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
149 sfr PCA0CPH2 = 0xEA; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
150 sfr PCA0CPL3 = 0xEB; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
151 sfr PCA0CPH3 = 0xEC; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
152 sfr PCA0CPL4 = 0xED; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
153 sfr PCA0CPH4 = 0xEE; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
154 sfr RSTSRC = 0xEF; /* RESET SOURCE */
155 sfr B = 0xF0; /* B REGISTER */
156 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
157 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
158 sfr SPI0CN = 0xF8; /* SPI 0 CONTROL */
159 sfr P7 = 0xF8; /* PORT 7 */
160 sfr PCA0L = 0xF9; /* PCA 0 TIMER - LOW BYTE */
161 sfr PCA0H = 0xFA; /* PCA 0 TIMER - HIGH BYTE */
162 sfr PCA0CPL0 = 0xFB; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
163 sfr PCA0CPH0 = 0xFC; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
164 sfr PCA0CPL1 = 0xFD; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
165 sfr PCA0CPH1 = 0xFE; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
166 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
167
168
169 /* BIT Registers */
170
171 /* TCON 0x88 */
172 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
173 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
174 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
175 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
176 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
177 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
178 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
179 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
C51 COMPILER V8.02 C8051F120 07/24/2008 14:18:51 PAGE 4
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