dianzizhong.txt

用vhdl编写的简易电子中设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity  dzz is
geniric(n: integer :=4 ;m: integer :=3);
port( clk_1s, clk : in std_logic;
      rst : in std_logic;
      led8 : out std_logic_vector(n-1 downto 0);
      sel  : out std_logic_vector(m-1 downto 0);
      pout : out std_logic);
end dzz;
------------------------------------------------
architecture one of dzz is
signal mh_l ,sh_l : integer range 0 to 59;
signal hh_l : integer range 0 to 23;
signal selh_l : std_logic_vector(2 downto 0);
signal ledhh,ledmh,ledsh : std_logic_vector(3 downto 0);
signal ledhl,ledml,ledsl : std_logic_vector(3 downto 0);
signal p_out : std_logic_vector(3 downto 0);
begin
s_1: process(clk_1s,rst)
  begin
   if rst='1' then
     mh_l<=0; sh_l<=0; hh_l<=0;
   elsif clk_1s'event and clk_1s='1' then
     if sh_l=59 then 
       if mh_l=59 then
         if hh_l=23 then
            hh_l<=0;
         else hh_l<=hh_l+1;
         end if;
         hm_l<=0;
       else hm_l<=mh_l+1;
       end if;
      sh_l<=0;
     else sh_l<=sh_l+1;
    end if;
 -- pout<='1' when hh_l=23 and mh_l=59 and sh_l=59 else '0';
     if hh_l=23 and mh_l=59 and sh_l=59 then pout<='1';
     else pout<='0';
     end if;
   end if;
 end process s_1;
------------------------------------------------
s_2: process(hh_l)
  begin
   case hh_l is
      when 00|01|02|03|04|05|06|07|08|09 => ledhh<="0000";
      when 10|11|12|13|14|15|16|17|18|19 => ledhh<="0001";
      when 20|21|22|23                   => ledhh<="0010";
      when others                        => ledhh<="0000";
   end case;
    case hh_l is 
      when 00|10|20    => ledhl<="0000";
      when 01|11|21    => ledhl<="0001";
      when 02|12|22    => ledhl<="0010"; 
      when 03|13|23    => ledhl<="0011"; 
      when 04|14|24    => ledhl<="0100"; 
      when 05|15|25    => ledhl<="0101"; 
      when 06|16|26    => ledhl<="0110";
      when 07|17|27    => ledhl<="0111";
      when 08|18|28    => ledhl<="0100";
      when 09|19|29    => ledhl<="1001";
      when others      => ledhl<="0000";
    end case;
  
end process s_2;
--------------------------------------------------
s_3: process(mh_l)
  begin
     case mh_l is
      when 00|01|02|03|04|05|06|07|08|09 => ledmh<="0000";
      when 10|11|12|13|14|15|16|17|18|19 => ledmh<="0001";
      when 20|21|22|23|24|25|26|27|28|29 => ledmh<="0010";
      when 30|31|32|33|34|35|36|37|38|39 => ledmh<="0011";
      when 40|41|42|43|44|45|46|47|48|49 => ledmh<="0100";
      when 50|51|52|53|54|55|56|57|58|59 => ledmh<="0101";
      when others =>ledmh<="0000";
     end case;
     case mh_l is
      when 00|10|20|30|40|50 =>ledml<="0000";
      when 01|11|21|31|41|51 =>ledml<="0001";
      when 02|12|22|32|42|52 =>ledml<="0010";
      when 03|13|23|33|43|53 =>ledml<="0011";
      when 04|14|24|34|44|54 =>ledml<="0100";
      when 05|15|25|35|45|55 =>ledml<="0101";
      when 06|16|26|36|46|56 =>ledml<="0110";
      when 07|17|27|37|47|57 =>ledml<="0111";
      when 08|18|28|38|48|58 =>ledml<="1000";
      when 09|19|29|39|49|59 =>ledml<="1001";
      when others =>ledml<="0000";
     end case;
end process s_3;
---------------------------------------------
s_4: process(sh_l)
 begin
   case sh_l is
      when 00|01|02|03|04|05|06|07|08|09 => ledsh<="0000";
      when 10|11|12|13|14|15|16|17|18|19 => ledsh<="0001";
      when 20|21|22|23|24|25|26|27|28|29 => ledsh<="0010";
      when 30|31|32|33|34|35|36|37|38|39 => ledsh<="0011";
      when 40|41|42|43|44|45|46|47|48|49 => ledsh<="0100";
      when 50|51|52|53|54|55|56|57|58|59 => ledsh<="0101";
      when others =>ledsh<="0000";
     end case;
     case sh_l is
      when 00|10|20|30|40|50 =>ledsl<="0000";
      when 01|11|21|31|41|51 =>ledsl<="0001";
      when 02|12|22|32|42|52 =>ledsl<="0010";
      when 03|13|23|33|43|53 =>ledsl<="0011";
      when 04|14|24|34|44|54 =>ledsl<="0100";
      when 05|15|25|35|45|55 =>ledsl<="0101";
      when 06|16|26|36|46|56 =>ledsl<="0110";
      when 07|17|27|37|47|57 =>ledsl<="0111";
      when 08|18|28|38|48|58 =>ledsl<="1000";
      when 09|19|29|39|49|59 =>ledsl<="1001";
      when others =>ledsl<="0000";
     end case;   
end process s_4;
--------------------------------------------------------
show : process(clk,selh_l)  
  begin
   if rst ='1' then selh_l<="000";
    elsif clk'event and clk='1' then
      if selh_l="101" then selh_l<="000";
      else selh_l<=selh_l+1;
      end if;
      case selh_l is
       when "000" => p_out <=ledhh;
       when "001" => p_out <=ledhl;
       when "010" => p_out <=ledmh;
       when "011" => p_out <=ledml;
       when "100" => p_out <=ledsh;
       when "101" => p_out <=ledsl;
       when others => p_out <=(others=>'0');
      end case;
   end if;
end process show;
---------------------------------------------------------
sel<=selh_l;
led8<=p_out;
---------------------------------------------------------
end one;