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19.2.3 Interface example using a generic bundle</div>
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A module header can be created with an unspecified interface reference as a place-holder for an interface to be selected when the module itself is instantiated. The unspecified interface is referred to as a “generic” interface reference. </p>
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This generic interface reference can only be declared by using the list of port declaration style of reference. It shall be illegal to declare such a generic interface reference using the old Verilog-1995 list of port style. </p>
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The following interface example shows how to specify a generic interface reference in a module definition. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00831"><pre class="Element12">// memMod and cpuMod can use any interface
module memMod (interface a, input bit clk);
...
endmodule
module cpuMod(interface b, input bit clk);
...
endmodule
interface simple_bus; // Define the interface
logic req, gnt;
logic [7:0] addr, data;
logic [1:0] mode;
logic start, rdy;
endinterface: simple_bus
module top;
logic clk = 0;
simple_bus sb_intf(); // Instantiate the interface
// Reference the sb_intf instance of the simple_bus
// interface from the generic interfaces of the
// memMod and cpuMod modules
memMod mem (.a(sb_intf), .clk(clk));
cpuMod cpu (.b(sb_intf), .clk(clk));
endmodule</pre></div></div>
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An implicit port cannot be used to reference a generic interface. A named port must be used to reference a generic interface, as shown below. </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00832"><pre class="Element12">module memMod (interface a, input bit clk);
...
endmodule
module cpuMod (interface b, input bit clk);
...
endmodule
module top;
logic clk = 0;
simple_bus sb_intf();
memMod mem (.*, .a(sb_intf)); // partial implicit port connections
cpuMod cpu (.*, .b(sb_intf)); // partial implicit port connections
endmodule</pre></div></div>
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