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<a href="#" onmousedown="showPopup(this, 'popup00427');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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20.4.2 Automatic bin creation for coverage points</div>
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If a coverage point does not define any bins, SystemVerilog automatically creates state bins. This provides an easy-to-use mechanism for binning different values of a coverage point. Users can either let the tool automatically create state bins for coverage points or explicitly define named bins for each coverage point. </p>
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When the automatic bin creation mechanism is used, SystemVerilog creates N bins to collect the sampled values of a coverage point. The value N is determined as follows:
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<li class="Element607">For an enum coverage point, N is the cardinality of the enumeration.</li>
<li class="Element607">For any other integral coverage point, N is the minimum of 2M and the value of the auto_bin_max option, where M is the number of bits needed to represent the coverage point.</li>
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If the number of automatic bins is smaller than the number of possible values (N < 2M ) then the 2M values are uniformly distributed in the N bins. If the number of values, 2M,is not divisible by N, then the last bin will include the additional (up to N-1) remaining items. For example, if M is 3, and N is 3 then the 8 possible values are distributed as follows: <0:1> ,<2:3>,<4,5,6,7>. </p>
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Automatically created bins only consider 2-state values; sampled values containing X or Z are excluded. </p>
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SystemVerilog implementations can impose a limit on the number of automatic bins. See the Section 20.6 for the default value of auto_bin_max. </p>
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Each automatically created bin will have a name of the form: auto[value], where value is either a single coverage point value, or the range of coverage point values included in the bin—in the form low:high. For enumerated types, value is the named constant associated with a particular enumerated value.</p></div>
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