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<a href="00871.html" target="topic">第十五章 时钟控制块</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00310');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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15.11 缺省时钟控制</div>
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一个时钟控制可以被说明成缺省的，这样它可以作用于一个指定模块、接口、或程序内的所有周期延时操作。 </p>
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缺省周期说明语句的语法如下： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00546"><pre class="Element12">module_or_generate_item_declaration ::= <span style="color: #008000">// 引用自附录A.1.5</span>
...
| <strong><span style="color: #FF0000">default clocking</span></strong> clocking_identifier<strong><span style="color: #FF0000">;</span></strong>
clocking_declaration ::= <span style="color: #008000">// 引用自附录A.6.11</span>
[<strong><span style="color: #FF0000">default</span></strong>] clocking [clocking_identifier] clocking_event<strong><span style="color: #FF0000">;</span></strong>
{clocking_item}
<strong><span style="color: #FF0000">endclocking</span></strong> [<strong><span style="color: #FF0000">:</span></strong> clocking_identifier]</pre></div></div>
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<strong>语法 15-3 — 缺省时钟控制语法（摘录自附录A）</strong></p><p class="Element10">
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<span class="Element146">clocking_identifier</span>必须是时钟控制块的名字。 </p>
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在一个程序、模块或接口中只能指定一个缺省时钟控制。在相同的程序或模块中多次指定一个缺省时钟控制应该导致一个编译器错误。 </p>
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一个缺省时钟控制仅在包含缺省时钟控制说明的范围内有效。这个范围包括包含了声明的模块、接口或程序以及任何嵌套的模块或接口。它不包括被实例化的模块或接口。 </p>
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例子1：将一个时钟控制声明成缺省的。 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00547"><pre class="Element12"><span style="color: #0000FF">program</span> test<span style="color: #800080">(</span><span style="color: #0000FF">input bit</span> clk<span style="color: #800080">,</span> <span style="color: #0000FF">input reg</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> data<span style="color: #800080">);</span>
<span style="color: #0000FF">default clocking</span> bus <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> clk<span style="color: #800080">);</span>
<span style="color: #0000FF">inout</span> data<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF"> initial begin</span>
<span style="color: #800080">## </span><span style="color: #FF0000">5</span><span style="color: #800080">;</span>
<span style="color: #0000FF">if</span> <span style="color: #800080">(</span>bus<span style="color: #800080">.</span>data <span style="color: #800080">== </span><span style="color: #FF0000">10</span><span style="color: #800080">)</span>
<span style="color: #800080">## </span><span style="color: #FF0000">1</span><span style="color: #800080">;</span>
<span style="color: #0000FF">else</span>
...
<span style="color: #0000FF">end</span>
<span style="color: #0000FF">endprogram</span></pre></div></div>
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例子2：将一个现存的时钟控制指定成缺省的。 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00548"><pre class="Element12"><span style="color: #0000FF">module</span> processor ...
<span style="color: #0000FF">clocking</span> busA <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> clk1<span style="color: #800080">);</span>
...
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF"> clocking</span> busB <span style="color: #800080">@(</span><span style="color: #0000FF">negedge</span> clk2<span style="color: #800080">);</span>
...
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF"> module</span> cpu <span style="color: #800080">(</span><span style="color: #0000FF">interface</span> y<span style="color: #0000FF">);</span>
<span style="color: #0000FF"> default clocking</span> busA<span style="color: #800080">;</span>
<span style="color: #0000FF">initial</span> <span style="color: #0000FF">begin</span>
<span style="color: #800080">## </span><span style="color: #FF0000">5</span><span style="color: #800080">;</span> <span style="color: #008000">// 使用busA => (posedge clk1)</span>
...
<span style="color: #0000FF">end</span>
<span style="color: #0000FF"> endmodule</span>
<span style="color: #0000FF">endmodule</span></pre></div></div>
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<a href="00871.html" target="topic">第十五章 时钟控制块</a></p></div>
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