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📁 这是一本关于verilog编程语言的教程,对学习verilog语言有帮助
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<a href="00873.html" target="topic">第十章 任务与函数</a>, <a href="00922.html" target="topic">主题</a></div>
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<a href="#" onmousedown="showPopup(this, 'popup00178');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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10.3 函数</div>
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<div class="Element13"><div class="Element12" id="code00317"><pre class="Element12">function_data_type ::= data_type | <strong><span style="color: #FF0000">void       </span><span style="color: #008000"></strong>// 引用自附录A.2.6</span>

function_data_type_or_implicit ::=
    function_data_type
  | [signing] {packed_dimension}

function_declaration ::= <strong><span style="color: #FF0000">function</span></strong> [lifetime] function_body_declaration

function_body_declaration ::=
    function_data_type_or_implicit
        [interface_identifier<strong><span style="color: #FF0000">.</span></strong>|class_scope]function_identifier<strong><span style="color: #FF0000">;</span></strong>
    {tf_item_declaration}
    {function_statement_or_null}
    <strong><span style="color: #FF0000">endfunction</span></strong> [<strong><span style="color: #FF0000">:</span></strong> function_identifier]
  | function_data_type_or_implicit
    [interface_identifier<strong><span style="color: #FF0000">.</span></strong>|class_scope] function_identifier <strong><span style="color: #FF0000">(</span></strong>[tf_port_list]<strong><span style="color: #FF0000">);</span></strong>
    {block_item_declaration}
    {function_statement_or_null}
    <strong><span style="color: #FF0000">endfunction</span></strong> [<strong><span style="color: #FF0000">:</span></strong> function_identifier]

lifetime ::= <strong><span style="color: #FF0000">static</span></strong> | <strong><span style="color: #FF0000">automatic      </span><span style="color: #008000"></strong>// 引用自附录A.2.1.3</span>

signing ::= <strong><span style="color: #FF0000">signed</span></strong> | <strong><span style="color: #FF0000">unsigned        </span><span style="color: #008000"></strong>// 引用自附录A.2.2.1</span></pre></div></div>
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<strong>语法10-2 — 函数语法（摘录自附录A）</strong></p><p class="Element10">
&nbsp;</p>
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Verilog函数声明或者在圆括号（向ANSI C一样）中，或者在声明和方向中具有形式参数。 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00318"><pre class="Element12"><span style="color: #0000FF">function logic</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> myfunc1<span style="color: #800080">(</span><span style="color: #0000FF">int</span> x<span style="color: #800080">,</span> <span style="color: #0000FF">int</span> y<span style="color: #800080">);</span>
    ...
<span style="color: #0000FF">endfunction</span>

<span style="color: #0000FF">function logic</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> myfunc2<span style="color: #800080">;</span>
    <span style="color: #0000FF">input int</span> x<span style="color: #800080">;</span>
    <span style="color: #0000FF">input int</span> y<span style="color: #800080">;</span>
    ...
<span style="color: #0000FF">endfunction</span></pre></div></div>
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SystemVerilog扩展了Verilog函数的能力，它允许函数具有与任务相同的形式参数。函数参数的方向如下： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00319"><pre class="Element12"><span style="color: #0000FF">input</span>   <span style="color: #008000">// 在开始的时候拷贝值</span>
<span style="color: #0000FF">output</span>  <span style="color: #008000">// 在结束的时候拷贝值</span>
<span style="color: #0000FF">inout</span>   <span style="color: #008000">// 在开始的时候拷贝，在结束的时候输出</span>
<span style="color: #0000FF">ref</span>     <span style="color: #008000">// 传递引用（参见</span><a href="00007.html" target="topic">10.4.2节</a><span style="color: #008000">）</span></pre></div></div>
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如果在函数声明中没有指定形式参数的方向，那么形式参数的缺省方向是输入。一旦指定了一个方向，那么它就成为后续参数的缺省方向。在下面的例子中，形式参数<i>a</i>和<i>b</i>缺省为输入，<i>u</i>和<i>v</i>都是输出： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00320"><pre class="Element12"><span style="color: #0000FF">function logic</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> myfunc3<span style="color: #800080">(</span><span style="color: #0000FF">int</span><span style="color: #800080"> </span>a<span style="color: #800080">,</span> <span style="color: #0000FF">int</span> b<span style="color: #800080">,</span> <span style="color: #0000FF">output logic</span> <span style="color: #800080">[</span><span style="color: #FF0000">15</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> u<span style="color: #800080">,</span> v<span style="color: #800080">);</span>
    ...
<span style="color: #0000FF">endfunction</span></pre></div></div>
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每一个形式参数都具有一个数据类型，它或者显式声明，或者从一个缺省类型继承。SystemVerilog中任务参数的缺省类型为<span style="color: #0000FF">logic</span>，它与Verilog兼容。SystemVerilog允许将一个数组声明成函数的一个形式参数，例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00321"><pre class="Element12"><span style="color: #0000FF">function</span> <span style="color: #800080">[</span><span style="color: #FF0000">3</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">][</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> myfunc4<span style="color: #800080">(</span><span style="color: #0000FF">input</span> <span style="color: #800080">[</span><span style="color: #FF0000">3</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">][</span><span style="color: #FF0000">7</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]</span> a<span style="color: #800080">,</span> b<span style="color: #800080">[</span><span style="color: #FF0000">3</span><span style="color: #800080">:</span><span style="color: #FF0000">0</span><span style="color: #800080">]);</span>
    ...
<span style="color: #0000FF">endfunction</span></pre></div></div>
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在一个事件表达式中、一个过程连续赋值语句内的表达式中、或者不在一个过程语句中的表达式中调用具有<span style="color: #0000FF">output</span>、<span style="color: #0000FF">inout</span>或<span style="color: #0000FF">ref</span>形式参数的函数是非法的。然而，在这些关联文中将<span style="color: #0000FF">const ref</span>作为函数参数是合法的（参见<a href="00007.html" target="topic">10.4.2节</a>）。&nbsp;</p>
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&nbsp;</p>
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SystemVerilog允许在函数头和<span style="color: #0000FF">endfunction</span>之间写入多条语句，这也就意味着<span style="color: #0000FF">begin</span>...<span style="color: #0000FF">end</span>可以被忽略。如果<span style="color: #0000FF">begin</span>...<span style="color: #0000FF">end</span>被忽略，这些语句顺序地执行，这与它们被包含在<span style="color: #0000FF">begin</span>...<span style="color: #0000FF">end</span>组中是一样的。任务中没有任何语句也是合法的，在这种情况下，函数返回与函数具有相同名字的隐含变量的当前值。</p></div>
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<a href="00873.html" target="topic">第十章 任务与函数</a></p></div>
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<a href="00003.html" target="topic">10.3.1 返回值与void函数</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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在Verilog中，函数必须具有返回值。返回值是通过为函数的名字赋值来完成的。 &nbsp;</div></td></tr><tr>
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<a href="00004.html" target="topic">10.3.2 丢弃函数返回值</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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在Verilog-2001中，函数返回的值必须使用在赋值语句或使用在一个表达式中。调用一个好象没有返回值的函数会导致一个警告信息。通过将函数返回值强制转换成<span style="color: #0000FF">void</span>类型，SystemVerilog允许使用<span style="color: #0000FF">void</span>数据类型来忽略一个函数的返回值。 &nbsp;</div></td></tr></table></div></div>
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