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<a href="#" onmousedown="showPopup(this, 'popup00016');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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3.3.3 有符号与无符号数据类型</div>
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整数类型使用整数算术，并且可以是有符号的也可以是无符号的。这些会影响某些操作码的含义，例如“<span style="color: #800080"><</span>”等。 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00018"><pre class="Element12"><span style="color: #0000FF">int</span> <span style="color: #0000FF">unsigned</span> ui<span style="color: #800080">;</span>
<span style="color: #0000FF">int</span> <span style="color: #0000FF">signed</span> si<span style="color: #800080">;</span></pre></div></div>
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缺省情况下，<span style="color: #0000FF">byte</span>、<span style="color: #0000FF">shortint</span>、<span style="color: #0000FF">int</span>、<span style="color: #0000FF">integer</span>和<span style="color: #0000FF">longint</span>是有符号的。<span style="color: #0000FF">bit</span>、<span style="color: #0000FF">reg</span>、<span style="color: #0000FF">logic</span>以及这几种类型的数组在缺省情况下是无符号的。 </p>
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注意：<span style="color: #0000FF">signed</span>关键字是Verilog-2001的一部分。<span style="color: #0000FF">unsigned</span>关键字在Verilog-2001中是保留关键字，但未被使用。 </p>
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参看第七章中有关操作码和表达式的说明。</p></div>
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