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7.10.1 内建包</div>
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SystemVerilog提供了一个内建的包，它包含了系统类型（例如类）、变量、任务和函数。用户不能在内建包中插入其它的声明。 内建包被隐含地导入到每一个编译单元的作用范围内（参见<a href="00206.html" target="topic">18.3节</a>）。因此，内建包中的声明在所有范围内直接有效（就像系统任务和函数一样），除非他们被用户代码重新定义。 </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00217"><pre class="Element12">built_in_data_type ::= [<strong><span style="color: #FF0000">std::</span></strong>] data_type_identifier <span style="color: #008000">// 未包含在附录A中</span>
built_in_function_call ::= [<strong><span style="color: #FF0000">std::</span></strong>] built_in_identifier <span style="color: #008000">// 未包含在附录A中</span></pre></div></div>
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包名字<span style="color: #0000FF">std</span>后面紧跟着范围解析操作符<span style="color: #800080">::</span>可以用来明确地访问内建包中的名字。例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00218"><pre class="Element12"><span style="color: #0000FF">std</span><span style="color: #800080">::</span>sys_task<span style="color: #800080">();</span> <span style="color: #008000">// 明确调用系统提供的sys_task</span></pre></div></div>
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与系统任务和函数不同，内建包中的任务和函数不需要使用<span style="color: #0000FF">$</span>前缀来避免与用户定义标识符的冲突。这种机制能够对语言以后向兼容的方式进行功能扩展，而无需加入额外的关键字或干扰本地命名空间。</p></div>
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