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18.12.1 变量的端口连接规则</div>
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如果一个端口声明具有一个变量数据类型，那么它的方向控制端口实例如何连接，变量的端口连接规则如下：
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<li class="Element606">一个输入端口可以连接到一个兼容类型的任意表达式。A continuous assignment shall be implied when a variable is connected to an input port declaration. Assignments to variables declared as an input port shall be illegal. If left unconnected, the port shall have the default initial value corresponding to the data type.</li>
<li class="Element606">An output port can be connected to a variable (or a concatenation) of a compatible data type. A continuous assignment shall be implied when a variable is connected the output port of an instance. Procedural or continuous assignments to a variable connected to the output port of an instance shall be illegal.</li>
<li class="Element606">An output port can be connected to a net (or a concatenation) of a compatible data type. In this case, multiple drivers shall be permitted on the net as in Verilog-2001.</li>
<li class="Element606">A variable data type is not permitted on either side of an inout port.</li>
<li class="Element606">A ref port shall be connected to an equivalent variable data type. References to the port variable shall be treated as hierarchal references to the variable it is connected to in its instantiation. This kind of port cannot be left unconnected. See Section 5.8.1, Equivalent types.</li>
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