frediv.v

来自「有关verilog的硬件实现VGA设计的代码。」· Verilog 代码 · 共 10 行

//Verilog Frequency Div. 2
module frediv(clk,out);
input clk;
output out;
reg out;
always @(posedge clk)
         out=(~out);
endmodule