bitmlt.tdf

乘法器的vhdl语言描述.本人调试已经通过

%
Bit serial multiplier - inspired by the work of Ray Andraka.

This module was written by steven groom ([e-mail]) and may be
freely used as and when necessary as long as this message remains intact.
%
include "bitadd.inc";
parameters
(
	width=16	-- the width of the parallel side
);
subdesign bitmlt
(
	dataa[width-1..0]		:	input;		-- parallel data in
	datab					:	input;		-- serial data in
	result					:	output;		-- serial result out
	clk						:	input;		-- module clock
	reset					:	input;		-- global reset
)
variable
	fn_add[width-2..0]		:	bitadd;		-- serial adder
	latency					:	dff;
begin
	latency=datab and dataa[width-1];
	latency.clk=clk;
	latency.clrn=not reset;
	fn_add[width-2].datab=latency;
	fn_add[width-2].dataa=datab and dataa[width-2];
	fn_add[width-2].clk=clk;
	fn_add[width-2].reset=reset;
	for i in width-3 to 0 generate
		fn_add[i].dataa=dataa[i] and datab;
		fn_add[i].datab=fn_add[i+1].result;
		fn_add[i].clk=clk;
		fn_add[i].reset=reset;
	end generate;
	result=fn_add[0].result;
end;