mlt.tdf

乘法器的vhdl语言描述.本人调试已经通过

%
This module was written by steven groom ([e-mail]) and may be used
as and where necessary as long as this message remains here.

for flex 8k this module had the following performance compiled as normal
	8x8		64LE
	16x16	122LE
	32x32	236LE

for max the following
	8x8		53LE
	16x16	102LE
	32x32	199LE
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include "lpm_counter";
include "bitmlt.inc";		-- bit serial multiplier
include "bitadd.inc";		-- bit serial adder
parameters
(
	widtha=12,
	widthb=12
);
constant width=ceil(log2(widtha+widthb));
subdesign mlt
(
	dataa[widtha-1..0]			:	input;
	datab[widthb-1..0]			:	input;
	clk							:	input;		-- clock for loading data registers
	ena							:	input;		-- enable for reg_a
	enb							:	input;		-- enable for reg_b
	go							:	input;		-- do a multiply on +ve edge
	busy						:	output;		-- activity flag
	clock						:	input;		-- module clock
	result[widtha+widthb-1..0]	:	output;		-- the result
)
variable
	sm							:	machine with states (idle,mult);

	fn_mult						:	bitmlt with (width=widthb);
	fn_counter					:	lpm_counter with (lpm_width=width);

	reg_a[widtha-1..0]			:	dffe;
	reg_b[widthb-1..0]			:	dffe;
	result[widtha+widthb-1..0]	:	dff;
	flag						:	dff;
begin
	defaults
		flag.clrn=vcc;
	end defaults;

	-- handle the start condition
	flag=vcc;
	flag.clk=go;

	-- hook up the serial multiplier
	fn_mult.dataa[]=reg_a[];
	fn_mult.datab=reg_b[0];

	-- handle the result shift register
	result[widtha+widthb-2..0]=result[widtha+widthb-1..1];
	result[widtha+widthb-1]=fn_mult.result;

	-- handle the state machine
	sm.clk=global(clock);
	case sm is
		when idle =>

			-- hold bit counter and multplier reset while idle
			fn_counter.aclr=vcc;
			fn_mult.reset=vcc;

			-- handle writing to input registers
			reg_a[]=dataa[];
			reg_b[]=datab[];
			reg_a[].clk=clk;
			reg_b[].clk=clk;
			reg_a[].ena=ena;
			reg_b[].ena=enb;

			-- advance the state machine on start condition
			if flag then
				sm=mult;
			end if;
		when mult =>

			-- while in multiply mode, allow reg_b to shift
			reg_b[].ena=vcc;
			reg_b[widthb-2..0]=reg_b[widthb-1..1];
			reg_b[].clk=clock;

			-- run the bit counter
			fn_counter.clock=clock;
			fn_mult.clk=clock;

			-- reset the flag
			flag.clrn=gnd;

			-- we are busy - for now...
			busy=vcc;

			-- shift the result
			result[].clk=clock;

			-- exit this state when bit count complete
			if fn_counter.q[]==(widtha+widthb) then
				sm=idle;
			end if;
	end case;
end;