__projnav.log

一个在Xilinx spartan3实现的时钟

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
...............
Phase 5.8 (Checksum:9a8eb2) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file clockcore.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 901 unrouted;       REAL time: 3 secs 

Phase 2: 830 unrouted;       REAL time: 4 secs 

Phase 3: 315 unrouted;       REAL time: 4 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 3 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|          b4_BUFGP       |  BUFGMUX0| No   |    2 |  0.000     |  0.305      |
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX1| No   |   20 |  0.121     |  0.459      |
+-------------------------+----------+------+------+------------+-------------+
|          b3_BUFGP       |  BUFGMUX2| No   |    3 |  0.000     |  0.311      |
+-------------------------+----------+------+------+------------+-------------+
|           daycbuf       |   Local  |      |    6 |  0.060     |  1.793      |
+-------------------------+----------+------+------+------------+-------------+
|             y2buf       |   Local  |      |    3 |  0.214     |  0.780      |
+-------------------------+----------+------+------+------------+-------------+
|             y3buf       |   Local  |      |    3 |  0.039     |  1.664      |
+-------------------------+----------+------+------+------------+-------------+
|             y4buf       |   Local  |      |    2 |  0.000     |  1.633      |
+-------------------------+----------+------+------+------------+-------------+
|           hclkbuf       |   Local  |      |    6 |  0.037     |  1.764      |
+-------------------------+----------+------+------+------------+-------------+
|            _n0144       |   Local  |      |    4 |  0.020     |  1.362      |
+-------------------------+----------+------+------+------------+-------------+
|           sclkbuf       |   Local  |      |    6 |  0.012     |  1.389      |
+-------------------------+----------+------+------+------------+-------------+
|           mclkbuf       |   Local  |      |    6 |  0.180     |  2.215      |
+-------------------------+----------+------+------+------------+-------------+
|           moncbuf       |   Local  |      |    6 |  0.057     |  1.623      |
+-------------------------+----------+------+------+------------+-------------+
|             y1buf       |   Local  |      |    3 |  0.019     |  1.982      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  68 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file clockcore.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Tue Jul 31 21:57:07 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module clockcore . . .
PAR command line: par -w -intstyle ise -ol std -t 1 clockcore_map.ncd clockcore.ncd clockcore.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "shake.v"
Module <noshake> compiled
Compiling source file "clockcore.v"
Module <clockcore> compiled
Compiling source file "clocktop.v"
Module <clocktop> compiled
No errors in compilation
Analysis of file <clocktop.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clocktop>.
Module <clocktop> is correct for synthesis.
 
Analyzing module <noshake>.
Module <noshake> is correct for synthesis.
 
Analyzing module <clockcore>.
Module <clockcore> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clockcore>.
    Related source file is clockcore.v.
WARNING:Xst:646 - Signal <yearten<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <min0> is assigned but never used.
WARNING:Xst:646 - Signal <min1> is assigned but never used.
WARNING:Xst:646 - Signal <yearls<3:2>> is assigned but never used.
WARNING:Xst:646 - Signal <sec0> is assigned but never used.
WARNING:Xst:646 - Signal <sec1> is assigned but never used.
WARNING:Xst:646 - Signal <monthmsb<3:1>> is assigned but never used.
    Found finite state machine <FSM_0> for signal <screen>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 4                                              |
    | Inputs             | 0                                              |
    | Outputs            | 3                                              |
    | Clock              | b4 (falling_edge)                              |
    | Reset              | b1 (negative)                                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 6                                              |
    | Inputs             | 1                                              |
    | Outputs            | 5                                              |
    | Clock              | b3 (falling_edge)                              |
    | Reset              | b1 (negative)                                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x8-bit ROM for signal <N>.
WARNING:Xst:737 - Found 4-bit latch for signal <pmask>.
    Found 4-bit comparator equal for signal <$n0023> created at line 336.
    Found 4-bit comparator equal for signal <$n0024> created at line 334.
    Found 4-bit adder for signal <$n0049> created at line 304.
    Found 4-bit adder for signal <$n0050> created at line 314.
    Found 4-bit adder for signal <$n0051> created at line 324.
    Found 4-bit adder for signal <$n0052> created at line 346.
    Found 1-bit xor2 for signal <$n0120> created at line 113.
    Found 1-bit xor3 for signal <bigmonth>.
    Found 4-bit up counter for signal <day>.
    Found 1-bit register for signal <dayc>.
    Found 4-bit 16-to-1 multiplexer for signal <dispdata>.
    Found 26-bit up counter for signal <divcounter>.
    Found 1-bit register for signal <hclk>.
    Found 4-bit register for signal <hour<1>>.
    Found 4-bit up counter for signal <hour<0>>.
    Found 1-bit register for signal <mclk>.
    Found 4-bit register for signal <min<1>>.
    Found 4-bit up counter for signal <min<0>>.
    Found 1-bit register for signal <monc>.
    Found 4-bit register for signal <month<1>>.
    Found 4-bit up counter for signal <month<0>>.
    Found 1-of-4 decoder for signal <ptmp>.
    Found 11-bit up counter for signal <scan>.
    Found 1-bit register for signal <sclk>.
    Found 4-bit register for signal <sec<1>>.
    Found 4-bit up counter for signal <sec<0>>.
    Found 4-bit up counter for signal <year>.
    Found 1-bit register for signal <year1c>.
    Found 1-bit register for signal <year2c>.
    Found 1-bit register for signal <year3c>.
    Found 1-bit register for signal <year4c>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred  12 Counter(s).
	inferred  17 D-type flip-flop(s).
	inferred   4 Adder/Subtracter(s).
	inferred   2 Comparator(s).
	inferred  20 Multiplexer(s).
	inferred   1 Decoder(s).
	inferred   1 Xor(s).
Unit <clockcore> synthesized.


Synthesizing Unit <noshake>.
    Related source file is shake.v.
WARNING:Xst:1780 - Signal <counten> is never used or assigned.
    Found 1-bit register for signal <noshakeb1>.
    Found 1-bit register for signal <noshakeb2>.
    Found 1-bit register for signal <noshakeb3>.
    Found 1-bit register for signal <noshakeb4>.
    Found 1-bit register for signal <sample>.
    Found 21-bit up counter for signal <shakecount>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <noshake> synthesized.


Synthesizing Unit <clocktop>.
    Related source file is clocktop.v.
Unit <clocktop> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 18
  1-bit register                   : 14
  4-bit register                   : 4
# Latches                          : 1
  4-bit latch                      : 1
# Counters                         : 13
  11-bit up counter                : 1
  4-bit up counter                 : 10
  21-bit up counter                : 1
  26-bit up counter                : 1
# Multiplexers                     : 9
  4-bit 16-to-1 multiplexer        : 1
  2-to-1 multiplexer               : 8
# Decoders                         : 1
  1-of-4 decoder                   : 1
# Adders/Subtractors               : 4
  4-bit adder                      : 4
# Comparators                      : 2
  4-bit comparator equal           : 2
# Xors                             : 2
  1-bit xor2                       : 1
  1-bit xor3                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <screen> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clocktop> ...

Optimizing unit <noshake> ...

Optimizing unit <clockcore> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clocktop, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     137  out of   3584     3%  
 Number of Slice Flip Flops:           141  out of   7168     1%  
 Number of 4 input LUTs:               247  out of   7168     3%  
 Number of bonded IOBs:                 16  out of    141    11%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 60    |
shake_sample:Q                     | NONE                   | 4     |
clockkernel_y1buf(clockkernel_y1buf:O)| NONE(*)(clockkernel_year_0_3)| 5     |