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一个在Xilinx spartan3实现的时钟

*                          HDL Compilation                              *
=========================================================================
Compiling source file "clockcore.v"
Module <clockcore> compiled
No errors in compilation
Analysis of file <clockcore.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clockcore>.
Module <clockcore> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clockcore>.
    Related source file is clockcore.v.
WARNING:Xst:646 - Signal <yearten<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <min0> is assigned but never used.
WARNING:Xst:646 - Signal <min1> is assigned but never used.
WARNING:Xst:646 - Signal <yearls<3:2>> is assigned but never used.
WARNING:Xst:646 - Signal <sec0> is assigned but never used.
WARNING:Xst:646 - Signal <sec1> is assigned but never used.
WARNING:Xst:646 - Signal <monthmsb<3:1>> is assigned but never used.
    Found finite state machine <FSM_0> for signal <screen>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 4                                              |
    | Inputs             | 0                                              |
    | Outputs            | 3                                              |
    | Clock              | b4 (falling_edge)                              |
    | Reset              | b1 (negative)                                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 6                                              |
    | Inputs             | 1                                              |
    | Outputs            | 5                                              |
    | Clock              | b3 (falling_edge)                              |
    | Reset              | b1 (negative)                                  |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x8-bit ROM for signal <N>.
WARNING:Xst:737 - Found 4-bit latch for signal <pmask>.
    Found 4-bit comparator equal for signal <$n0023> created at line 336.
    Found 4-bit comparator equal for signal <$n0024> created at line 334.
    Found 4-bit adder for signal <$n0049> created at line 304.
    Found 4-bit adder for signal <$n0050> created at line 314.
    Found 4-bit adder for signal <$n0051> created at line 324.
    Found 4-bit adder for signal <$n0052> created at line 346.
    Found 1-bit xor2 for signal <$n0120> created at line 113.
    Found 1-bit xor3 for signal <bigmonth>.
    Found 4-bit up counter for signal <day>.
    Found 1-bit register for signal <dayc>.
    Found 4-bit 16-to-1 multiplexer for signal <dispdata>.
    Found 26-bit up counter for signal <divcounter>.
    Found 1-bit register for signal <hclk>.
    Found 4-bit register for signal <hour<1>>.
    Found 4-bit up counter for signal <hour<0>>.
    Found 1-bit register for signal <mclk>.
    Found 4-bit register for signal <min<1>>.
    Found 4-bit up counter for signal <min<0>>.
    Found 1-bit register for signal <monc>.
    Found 4-bit register for signal <month<1>>.
    Found 4-bit up counter for signal <month<0>>.
    Found 1-of-4 decoder for signal <ptmp>.
    Found 11-bit up counter for signal <scan>.
    Found 1-bit register for signal <sclk>.
    Found 4-bit register for signal <sec<1>>.
    Found 4-bit up counter for signal <sec<0>>.
    Found 4-bit up counter for signal <year>.
    Found 1-bit register for signal <year1c>.
    Found 1-bit register for signal <year2c>.
    Found 1-bit register for signal <year3c>.
    Found 1-bit register for signal <year4c>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred  12 Counter(s).
	inferred  17 D-type flip-flop(s).
	inferred   4 Adder/Subtracter(s).
	inferred   2 Comparator(s).
	inferred  20 Multiplexer(s).
	inferred   1 Decoder(s).
	inferred   1 Xor(s).
Unit <clockcore> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 13
  1-bit register                   : 9
  4-bit register                   : 4
# Latches                          : 1
  4-bit latch                      : 1
# Counters                         : 12
  11-bit up counter                : 1
  4-bit up counter                 : 10
  26-bit up counter                : 1
# Multiplexers                     : 5
  4-bit 16-to-1 multiplexer        : 1
  2-to-1 multiplexer               : 4
# Decoders                         : 1
  1-of-4 decoder                   : 1
# Adders/Subtractors               : 4
  4-bit adder                      : 4
# Comparators                      : 2
  4-bit comparator equal           : 2
# Xors                             : 2
  1-bit xor2                       : 1
  1-bit xor3                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <screen> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clockcore> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clockcore, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     116  out of   3584     3%  
 Number of Slice Flip Flops:           115  out of   7168     1%  
 Number of 4 input LUTs:               210  out of   7168     2%  
 Number of bonded IOBs:                 14  out of    141     9%  
 Number of GCLKs:                        3  out of      8    37%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
y1buf(y1buf:O)                     | NONE(*)(year_0_0)      | 5     |
moncbuf(moncbuf:O)                 | NONE(*)(year1c)        | 9     |
daycbuf(daycbuf:O)                 | NONE(*)(day_0_0)       | 9     |
hclkbuf(hclkbuf:O)                 | NONE(*)(hour_1_0)      | 9     |
sclkbuf(sclkbuf:O)                 | NONE(*)(sec_1_2)       | 9     |
_n0144(_n01441:O)                  | NONE(*)(pmask_0)       | 4     |
y4buf(y4buf:O)                     | NONE(*)(year_3_1)      | 4     |
y3buf(y3buf:O)                     | NONE(*)(year_2_1)      | 5     |
y2buf(y2buf:O)                     | NONE(*)(year_1_0)      | 5     |
mclkbuf(mclkbuf:O)                 | NONE(*)(hclk)          | 9     |
clk                                | BUFGP                  | 38    |
b3                                 | BUFGP                  | 5     |
b4                                 | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+
(*) These 10 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.919ns (Maximum Frequency: 112.114MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.532ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
e:\hardware_projects\ise_projects\eternityclock/_ngo -i -p xc3s400-pq208-4
clockcore.ngc clockcore.ngd 

Reading NGO file "e:/hardware_projects/ise_projects/eternityclock/clockcore.ngc"
...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39748 kilobytes

Writing NGD file "clockcore.ngd" ...

Writing NGDBUILD log file "clockcore.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s400pq208-4".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Total Number Slice Registers:       115 out of   7,168    1%
    Number used as Flip Flops:                   111
    Number used as Latches:                        4
  Number of 4 input LUTs:             192 out of   7,168    2%
Logic Distribution:
  Number of occupied Slices:                          112 out of   3,584    3%
    Number of Slices containing only related logic:     112 out of     112  100%
    Number of Slices containing unrelated logic:          0 out of     112    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            202 out of   7,168    2%
  Number used as logic:                192
  Number used as a route-thru:          10
  Number of bonded IOBs:               17 out of     141   12%
  Number of GCLKs:                     3 out of       8   37%

Total equivalent gate count for design:  2,378
Additional JTAG gate count for IOBs:  816
Peak Memory Usage:  75 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "clockcore_map.mrp" for details.
Completed process "Map".

Mapping Module clockcore . . .
MAP command line:
map -intstyle ise -p xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -tx off -o clockcore_map.ncd clockcore.ngd clockcore.pcf
Mapping Module clockcore: DONE



Started process "Place & Route".





Constraints file: clockcore.pcf

Loading device database for application Par from file "clockcore_map.ncd".
   "clockcore" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Par from file '3s400.nph' in environment
D:/Xilinx.
Device speed data version:  PREVIEW 1.26 2003-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            17 out of 141    12%
      Number of LOCed External IOBs    0 out of 17      0%

   Number of SLICELs                 104 out of 3584    2%
   Number of SLICEMs                   8 out of 1792    1%

   Number of BUFGMUXs                  3 out of 8      37%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal day_0__n0001<3> has no load

Phase 1.1
Phase 1.1 (Checksum:989949) REAL time: 2 secs