__projnav.log

一个在Xilinx spartan3实现的时钟

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "shake.v"
Module <noshake> compiled
No errors in compilation
Analysis of file <noshake.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <noshake>.
Module <noshake> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <noshake>.
    Related source file is shake.v.
WARNING:Xst:1780 - Signal <counten> is never used or assigned.
    Found 1-bit register for signal <noshakeb1>.
    Found 1-bit register for signal <noshakeb2>.
    Found 1-bit register for signal <noshakeb3>.
    Found 1-bit register for signal <noshakeb4>.
    Found 1-bit register for signal <sample>.
    Found 21-bit up counter for signal <shakecount>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <noshake> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  1-bit register                   : 5
# Counters                         : 1
  21-bit up counter                : 1
# Multiplexers                     : 4
  2-to-1 multiplexer               : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <noshake> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block noshake, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      22  out of   3584     0%  
 Number of Slice Flip Flops:            26  out of   7168     0%  
 Number of 4 input LUTs:                36  out of   7168     0%  
 Number of bonded IOBs:                  8  out of    141     5%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 22    |
sample:Q                           | NONE                   | 4     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.336ns (Maximum Frequency: 119.962MHz)
   Minimum input arrival time before clock: 2.711ns
   Maximum output required time after clock: 6.271ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
e:\hardware_projects\ise_projects\eternityclock/_ngo -i -p xc3s400-pq208-4
noshake.ngc noshake.ngd 

Reading NGO file "e:/hardware_projects/ise_projects/eternityclock/noshake.ngc"
...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39748 kilobytes

Writing NGD file "noshake.ngd" ...

Writing NGDBUILD log file "noshake.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "shake.v"
Module <noshake> compiled
Compiling source file "clockcore.v"
Module <clockcore> compiled
Compiling source file "clocktop.v"
Module <clocktop> compiled
No errors in compilation
Analysis of file <clocktop.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <clocktop>.
Module <clocktop> is correct for synthesis.
 
Analyzing module <noshake>.
Module <noshake> is correct for synthesis.
 
Analyzing module <clockcore>.
Module <clockcore> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <clockcore>.
    Related source file is clockcore.v.
WARNING:Xst:646 - Signal <yearten<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <yearls<3:2>> is assigned but never used.
WARNING:Xst:646 - Signal <monthmsb<3:1>> is assigned but never used.
    Found 16x8-bit ROM for signal <N>.
WARNING:Xst:737 - Found 4-bit latch for signal <pmask>.
    Found 2-bit register for signal <screen>.
    Found 3-bit register for signal <state>.
    Found 11-bit up counter for signal <scan>.
    Found 4-bit comparator equal for signal <$n0017> created at line 342.
    Found 4-bit comparator equal for signal <$n0018> created at line 340.
    Found 4-bit adder for signal <$n0043> created at line 310.
    Found 4-bit adder for signal <$n0044> created at line 320.
    Found 4-bit adder for signal <$n0045> created at line 330.
    Found 4-bit adder for signal <$n0046> created at line 352.
    Found 1-bit xor2 for signal <$n0119> created at line 119.
    Found 1-bit xor3 for signal <bigmonth>.
    Found 4-bit up counter for signal <day>.
    Found 1-bit register for signal <dayc>.
    Found 4-bit 16-to-1 multiplexer for signal <dispdata>.
    Found 26-bit up counter for signal <divcounter>.
    Found 1-bit register for signal <hclk>.
    Found 4-bit register for signal <hour<1>>.
    Found 4-bit up counter for signal <hour<0>>.
    Found 1-bit register for signal <mclk>.
    Found 4-bit register for signal <min<1>>.
    Found 4-bit up counter for signal <min<0>>.
    Found 1-bit register for signal <monc>.
    Found 4-bit register for signal <month<1>>.
    Found 4-bit up counter for signal <month<0>>.
    Found 1-of-4 decoder for signal <ptmp>.
    Found 1-bit register for signal <sclk>.
    Found 4-bit register for signal <sec<1>>.
    Found 4-bit up counter for signal <sec<0>>.
    Found 4-bit up counter for signal <year>.
    Found 1-bit register for signal <year1c>.
    Found 1-bit register for signal <year2c>.
    Found 1-bit register for signal <year3c>.
    Found 1-bit register for signal <year4c>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred  12 Counter(s).
	inferred  22 D-type flip-flop(s).
	inferred   4 Adder/Subtracter(s).
	inferred   2 Comparator(s).
	inferred  20 Multiplexer(s).
	inferred   1 Decoder(s).
	inferred   1 Xor(s).
Unit <clockcore> synthesized.


Synthesizing Unit <noshake>.
    Related source file is shake.v.
WARNING:Xst:1780 - Signal <counten> is never used or assigned.
    Found 1-bit register for signal <noshakeb1>.
    Found 1-bit register for signal <noshakeb2>.
    Found 1-bit register for signal <noshakeb3>.
    Found 1-bit register for signal <noshakeb4>.
    Found 1-bit register for signal <sample>.
    Found 21-bit up counter for signal <shakecount>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <noshake> synthesized.


Synthesizing Unit <clocktop>.
    Related source file is clocktop.v.
Unit <clocktop> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Registers                        : 20
  1-bit register                   : 14
  2-bit register                   : 1
  3-bit register                   : 1
  4-bit register                   : 4
# Latches                          : 1
  4-bit latch                      : 1
# Counters                         : 13
  11-bit up counter                : 1
  4-bit up counter                 : 10
  21-bit up counter                : 1
  26-bit up counter                : 1
# Multiplexers                     : 9
  4-bit 16-to-1 multiplexer        : 1
  2-to-1 multiplexer               : 8
# Decoders                         : 1
  1-of-4 decoder                   : 1
# Adders/Subtractors               : 4
  4-bit adder                      : 4
# Comparators                      : 2
  4-bit comparator equal           : 2
# Xors                             : 2
  1-bit xor2                       : 1
  1-bit xor3                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clocktop> ...

Optimizing unit <noshake> ...

Optimizing unit <clockcore> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clocktop, actual ratio is 3.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     133  out of   3584     3%  
 Number of Slice Flip Flops:           137  out of   7168     1%  
 Number of 4 input LUTs:               241  out of   7168     3%  
 Number of bonded IOBs:                 51  out of    141    36%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+