clocktop.syr

一个在Xilinx spartan3实现的时钟

     MUXF6:S->O            1   0.869   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_2 (clockkernel_Mmux_dispdata__net22)
     MUXF7:I0->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     11.680ns (8.903ns logic, 2.777ns route)
                                       (76.2% logic, 23.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_mclkbuf1:O'
Offset:              10.659ns (Levels of Logic = 6)
  Source:            clockkernel_min_0_1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_mclkbuf1:O rising

  Data Path: clockkernel_min_0_1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             6   0.619   0.688  clockkernel_min_0_1 (clockkernel_min_0_1)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_291 (clockkernel_Mmux_dispdata__net16)
     MUXF5:I0->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_4 (clockkernel_Mmux_dispdata__net18)
     MUXF6:I0->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_2 (clockkernel_Mmux_dispdata__net22)
     MUXF7:I0->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.659ns (8.984ns logic, 1.675ns route)
                                       (84.3% logic, 15.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_sclkbuf1:O'
Offset:              10.629ns (Levels of Logic = 6)
  Source:            clockkernel_sec_0_1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_sclkbuf1:O rising

  Data Path: clockkernel_sec_0_1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.619   0.658  clockkernel_sec_0_1 (clockkernel_sec_0_1)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_301 (clockkernel_Mmux_dispdata__net17)
     MUXF5:I1->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_4 (clockkernel_Mmux_dispdata__net18)
     MUXF6:I0->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_2 (clockkernel_Mmux_dispdata__net22)
     MUXF7:I0->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.629ns (8.984ns logic, 1.645ns route)
                                       (84.5% logic, 15.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_hclkbuf1:O'
Offset:              10.659ns (Levels of Logic = 6)
  Source:            clockkernel_hour_0_1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_hclkbuf1:O rising

  Data Path: clockkernel_hour_0_1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             6   0.619   0.688  clockkernel_hour_0_1 (clockkernel_hour_0_1)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_311 (clockkernel_Mmux_dispdata__net19)
     MUXF5:I0->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_5 (clockkernel_Mmux_dispdata__net21)
     MUXF6:I1->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_2 (clockkernel_Mmux_dispdata__net22)
     MUXF7:I0->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.659ns (8.984ns logic, 1.675ns route)
                                       (84.3% logic, 15.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_moncbuf1:O'
Offset:              10.718ns (Levels of Logic = 6)
  Source:            clockkernel_month_0_0 (FF)
  Destination:       N<6> (PAD)
  Source Clock:      clockkernel_moncbuf1:O rising

  Data Path: clockkernel_month_0_0 to N<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             9   0.619   0.777  clockkernel_month_0_0 (clockkernel_month_0_0)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_251 (clockkernel_Mmux_dispdata__net8)
     MUXF5:I0->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_2 (clockkernel_Mmux_dispdata__net10)
     MUXF6:I0->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_1 (clockkernel_Mmux_dispdata__net14)
     MUXF7:I1->O           7   0.563   0.717  clockkernel_Mmux_dispdata_inst_mux_f7_0 (clockkernel_dispdata<0>)
     LUT4:I3->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.718ns (8.984ns logic, 1.734ns route)
                                       (83.8% logic, 16.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_daycbuf1:O'
Offset:              10.688ns (Levels of Logic = 6)
  Source:            clockkernel_day_0_3 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_daycbuf1:O rising

  Data Path: clockkernel_day_0_3 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             7   0.619   0.717  clockkernel_day_0_3 (clockkernel_day_0_3)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_501 (clockkernel_Mmux_dispdata__net54)
     MUXF5:I1->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_14 (clockkernel_Mmux_dispdata__net55)
     MUXF6:I0->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_7 (clockkernel_Mmux_dispdata__net59)
     MUXF7:I1->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_3 (clockkernel_dispdata<3>)
     LUT4:I2->O            1   0.720   0.240  clockkernel__n00891 (N_5_OBUF)
     OBUF:I->O                 5.412          N_5_OBUF (N<5>)
    ----------------------------------------
    Total                     10.688ns (8.984ns logic, 1.704ns route)
                                       (84.1% logic, 15.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_y3buf1:O'
Offset:              10.629ns (Levels of Logic = 6)
  Source:            clockkernel_year_2_1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_y3buf1:O rising

  Data Path: clockkernel_year_2_1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.619   0.658  clockkernel_year_2_1 (clockkernel_year_2_1)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_351 (clockkernel_Mmux_dispdata__net26)
     MUXF5:I0->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_7 (clockkernel_Mmux_dispdata__net28)
     MUXF6:I1->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_3 (clockkernel_Mmux_dispdata__net29)
     MUXF7:I1->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.629ns (8.984ns logic, 1.645ns route)
                                       (84.5% logic, 15.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_y4buf1:O'
Offset:              10.600ns (Levels of Logic = 6)
  Source:            clockkernel_year_3_1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_y4buf1:O rising

  Data Path: clockkernel_year_3_1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             4   0.619   0.629  clockkernel_year_3_1 (clockkernel_year_3_1)
     LUT3:I2->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_351 (clockkernel_Mmux_dispdata__net26)
     MUXF5:I0->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_7 (clockkernel_Mmux_dispdata__net28)
     MUXF6:I1->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_3 (clockkernel_Mmux_dispdata__net29)
     MUXF7:I1->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.600ns (8.984ns logic, 1.616ns route)
                                       (84.8% logic, 15.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_y1buf1:O'
Offset:              10.659ns (Levels of Logic = 6)
  Source:            clockkernel_year_0_1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clockkernel_y1buf1:O rising

  Data Path: clockkernel_year_0_1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             6   0.619   0.688  clockkernel_year_0_1 (clockkernel_year_0_1)
     LUT3:I1->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_361 (clockkernel_Mmux_dispdata__net27)
     MUXF5:I1->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_7 (clockkernel_Mmux_dispdata__net28)
     MUXF6:I1->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_3 (clockkernel_Mmux_dispdata__net29)
     MUXF7:I1->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.659ns (8.984ns logic, 1.675ns route)
                                       (84.3% logic, 15.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel_y2buf1:O'
Offset:              10.658ns (Levels of Logic = 6)
  Source:            clockkernel_year_1_0 (FF)
  Destination:       N<6> (PAD)
  Source Clock:      clockkernel_y2buf1:O rising

  Data Path: clockkernel_year_1_0 to N<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             7   0.619   0.717  clockkernel_year_1_0 (clockkernel_year_1_0)
     LUT3:I2->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_281 (clockkernel_Mmux_dispdata__net12)
     MUXF5:I1->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_3 (clockkernel_Mmux_dispdata__net13)
     MUXF6:I1->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_1 (clockkernel_Mmux_dispdata__net14)
     MUXF7:I1->O           7   0.563   0.717  clockkernel_Mmux_dispdata_inst_mux_f7_0 (clockkernel_dispdata<0>)
     LUT4:I3->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     10.658ns (8.984ns logic, 1.674ns route)
                                       (84.3% logic, 15.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'shake_noshakeb3:Q'
Offset:              9.808ns (Levels of Logic = 3)
  Source:            clockkernel_state_FFd1 (FF)
  Destination:       P<3> (PAD)
  Source Clock:      shake_noshakeb3:Q falling

  Data Path: clockkernel_state_FFd1 to P<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           17   0.619   1.031  clockkernel_state_FFd1 (clockkernel_state_FFd1)
     LUT4:I1->O           18   0.720   1.066  clockkernel__n01551 (clockkernel__n0155)
     LUT4:I2->O            1   0.720   0.240  clockkernel_P<3> (P_3_OBUF)
     OBUF:I->O                 5.412          P_3_OBUF (P<3>)
    ----------------------------------------
    Total                      9.808ns (7.471ns logic, 2.337ns route)
                                       (76.2% logic, 23.8% route)

=========================================================================
CPU : 19.92 / 20.83 s | Elapsed : 19.00 / 20.00 s
 
--> 

Total memory usage is 73776 kilobytes