clocktop.syr

一个在Xilinx spartan3实现的时钟

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_moncbuf1:O'
Delay:               5.181ns (Levels of Logic = 3)
  Source:            clockkernel_month_0_0 (FF)
  Destination:       clockkernel_month_0_1 (FF)
  Source Clock:      clockkernel_moncbuf1:O rising
  Destination Clock: clockkernel_moncbuf1:O rising

  Data Path: clockkernel_month_0_0 to clockkernel_month_0_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             9   0.619   0.777  clockkernel_month_0_0 (clockkernel_month_0_0)
     LUT4:I0->O            5   0.720   0.658  clockkernel_Ker86861 (clockkernel_N8688)
     LUT2:I1->O            2   0.720   0.465  clockkernel__n00261 (clockkernel__n0026)
     LUT4:I0->O            1   0.720   0.000  clockkernel_month_1_Mmux__n0001_Result<2>1 (clockkernel_month_1__n0001<2>)
     FDCE:D                    0.502          clockkernel_month_1_2
    ----------------------------------------
    Total                      5.181ns (3.281ns logic, 1.900ns route)
                                       (63.3% logic, 36.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_daycbuf1:O'
Delay:               6.229ns (Levels of Logic = 4)
  Source:            clockkernel_day_1_0 (FF)
  Destination:       clockkernel_day_1_1 (FF)
  Source Clock:      clockkernel_daycbuf1:O rising
  Destination Clock: clockkernel_daycbuf1:O rising

  Data Path: clockkernel_day_1_0 to clockkernel_day_1_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             8   0.619   0.747  clockkernel_day_1_0 (clockkernel_day_1_0)
     LUT2:I1->O            1   0.720   0.240  clockkernel__n018019 (CHOICE306)
     LUT4:I3->O            1   0.720   0.240  clockkernel__n018026 (CHOICE307)
     LUT4:I1->O            1   0.720   0.240  clockkernel__n018080 (CHOICE319)
     LUT4:I3->O            4   0.720   0.629  clockkernel__n0180102 (clockkernel__n0180)
     FDCE:CE                   0.634          clockkernel_day_1_2
    ----------------------------------------
    Total                      6.229ns (4.133ns logic, 2.096ns route)
                                       (66.4% logic, 33.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_hclkbuf1:O'
Delay:               5.151ns (Levels of Logic = 3)
  Source:            clockkernel_hour_0_0 (FF)
  Destination:       clockkernel_hour_0_1 (FF)
  Source Clock:      clockkernel_hclkbuf1:O rising
  Destination Clock: clockkernel_hclkbuf1:O rising

  Data Path: clockkernel_hour_0_0 to clockkernel_hour_0_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             7   0.619   0.717  clockkernel_hour_0_0 (clockkernel_hour_0_0)
     LUT4:I2->O            6   0.720   0.688  clockkernel__n01011 (clockkernel__n0101)
     LUT2:I1->O            2   0.720   0.465  clockkernel__n00181 (clockkernel__n0018)
     LUT4:I0->O            1   0.720   0.000  clockkernel_hour_1_Mmux__n0001_Result<2>1 (clockkernel_hour_1__n0001<2>)
     FDCE:D                    0.502          clockkernel_hour_1_2
    ----------------------------------------
    Total                      5.151ns (3.281ns logic, 1.870ns route)
                                       (63.7% logic, 36.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_mclkbuf1:O'
Delay:               5.092ns (Levels of Logic = 3)
  Source:            clockkernel_min_0_0 (FF)
  Destination:       clockkernel_hclk (FF)
  Source Clock:      clockkernel_mclkbuf1:O rising
  Destination Clock: clockkernel_mclkbuf1:O rising

  Data Path: clockkernel_min_0_0 to clockkernel_hclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             7   0.619   0.717  clockkernel_min_0_0 (clockkernel_min_0_0)
     LUT4:I2->O            4   0.720   0.629  clockkernel__n00161 (clockkernel__n0016)
     LUT4:I0->O            2   0.720   0.465  clockkernel__n0052 (clockkernel__n0052)
     LUT3:I2->O            1   0.720   0.000  clockkernel__n0015<2>1 (clockkernel__n0015<2>)
     FDCE:D                    0.502          clockkernel_min_1_2
    ----------------------------------------
    Total                      5.092ns (3.281ns logic, 1.811ns route)
                                       (64.4% logic, 35.6% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_y2buf1:O'
Delay:               3.518ns (Levels of Logic = 2)
  Source:            clockkernel_year_1_0 (FF)
  Destination:       clockkernel_year3c (FF)
  Source Clock:      clockkernel_y2buf1:O rising
  Destination Clock: clockkernel_y2buf1:O rising

  Data Path: clockkernel_year_1_0 to clockkernel_year3c
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             7   0.619   0.717  clockkernel_year_1_0 (clockkernel_year_1_0)
     LUT2:I1->O            1   0.720   0.240  clockkernel__n01522 (CHOICE264)
     LUT4:I1->O            1   0.720   0.000  clockkernel__n015232 (clockkernel__n0152)
     FDC:D                     0.502          clockkernel_year3c
    ----------------------------------------
    Total                      3.518ns (2.561ns logic, 0.957ns route)
                                       (72.8% logic, 27.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_y3buf1:O'
Delay:               3.459ns (Levels of Logic = 2)
  Source:            clockkernel_year_2_2 (FF)
  Destination:       clockkernel_year4c (FF)
  Source Clock:      clockkernel_y3buf1:O rising
  Destination Clock: clockkernel_y3buf1:O rising

  Data Path: clockkernel_year_2_2 to clockkernel_year4c
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.619   0.658  clockkernel_year_2_2 (clockkernel_year_2_2)
     LUT4:I3->O            1   0.720   0.240  clockkernel__n0153_SW0 (N12326)
     LUT4:I1->O            1   0.720   0.000  clockkernel__n0153 (clockkernel__n0153)
     FDC:D                     0.502          clockkernel_year4c
    ----------------------------------------
    Total                      3.459ns (2.561ns logic, 0.898ns route)
                                       (74.0% logic, 26.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_y4buf1:O'
Delay:               2.499ns (Levels of Logic = 1)
  Source:            clockkernel_year_3_0 (FF)
  Destination:       clockkernel_year_3_3 (FF)
  Source Clock:      clockkernel_y4buf1:O rising
  Destination Clock: clockkernel_y4buf1:O rising

  Data Path: clockkernel_year_3_0 to clockkernel_year_3_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             5   0.619   0.658  clockkernel_year_3_0 (clockkernel_year_3_0)
     LUT4:I1->O            1   0.720   0.000  clockkernel_year_3_Mmux__n0001_Result<3>1 (clockkernel_year_3__n0001<3>)
     FDCE:D                    0.502          clockkernel_year_3_3
    ----------------------------------------
    Total                      2.499ns (1.841ns logic, 0.658ns route)
                                       (73.7% logic, 26.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'shake_noshakeb3:Q'
Delay:               2.872ns (Levels of Logic = 1)
  Source:            clockkernel_state_FFd1 (FF)
  Destination:       clockkernel_state_FFd5 (FF)
  Source Clock:      shake_noshakeb3:Q falling
  Destination Clock: shake_noshakeb3:Q falling

  Data Path: clockkernel_state_FFd1 to clockkernel_state_FFd5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           17   0.619   1.031  clockkernel_state_FFd1 (clockkernel_state_FFd1)
     LUT3:I2->O            1   0.720   0.000  clockkernel_state_FFd5-In1 (clockkernel_state_FFd5-In)
     FDP_1:D                   0.502          clockkernel_state_FFd5
    ----------------------------------------
    Total                      2.872ns (1.841ns logic, 1.031ns route)
                                       (64.1% logic, 35.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'shake_noshakeb4:Q'
Delay:               2.016ns (Levels of Logic = 0)
  Source:            clockkernel_screen_FFd1 (FF)
  Destination:       clockkernel_screen_FFd4 (FF)
  Source Clock:      shake_noshakeb4:Q falling
  Destination Clock: shake_noshakeb4:Q falling

  Data Path: clockkernel_screen_FFd1 to clockkernel_screen_FFd4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           13   0.619   0.895  clockkernel_screen_FFd1 (clockkernel_screen_FFd1)
     FDP_1:D                   0.502          clockkernel_screen_FFd4
    ----------------------------------------
    Total                      2.016ns (1.121ns logic, 0.895ns route)
                                       (55.6% logic, 44.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'shake_sample:Q'
Offset:              3.291ns (Levels of Logic = 2)
  Source:            b4 (PAD)
  Destination:       shake_noshakeb2 (FF)
  Destination Clock: shake_sample:Q rising

  Data Path: b4 to shake_noshakeb2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   1.492   0.577  b4_IBUF (b4_IBUF)
     LUT2:I1->O            1   0.720   0.000  shake__n00031 (shake__n0003)
     FDP:D                     0.502          shake_noshakeb3
    ----------------------------------------
    Total                      3.291ns (2.714ns logic, 0.577ns route)
                                       (82.5% logic, 17.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              11.298ns (Levels of Logic = 6)
  Source:            clockkernel_scan_9 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      clk rising

  Data Path: clockkernel_scan_9 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             38   0.619   1.327  clockkernel_scan_9 (clockkernel_scan_9)
     LUT3:I0->O            1   0.720   0.000  clockkernel_Mmux_dispdata_inst_lut3_351 (clockkernel_Mmux_dispdata__net26)
     MUXF5:I0->O           1   0.387   0.000  clockkernel_Mmux_dispdata_inst_mux_f5_7 (clockkernel_Mmux_dispdata__net28)
     MUXF6:I1->O           1   0.563   0.000  clockkernel_Mmux_dispdata_inst_mux_f6_3 (clockkernel_Mmux_dispdata__net29)
     MUXF7:I1->O           8   0.563   0.747  clockkernel_Mmux_dispdata_inst_mux_f7_1 (clockkernel_dispdata<1>)
     LUT4:I1->O            1   0.720   0.240  clockkernel_N<3>1 (N_3_OBUF)
     OBUF:I->O                 5.412          N_3_OBUF (N<3>)
    ----------------------------------------
    Total                     11.298ns (8.984ns logic, 2.314ns route)
                                       (79.5% logic, 20.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'shake_noshakeb4:Q'
Offset:              11.680ns (Levels of Logic = 5)
  Source:            clockkernel_screen_FFd1 (FF)
  Destination:       N<7> (PAD)
  Source Clock:      shake_noshakeb4:Q falling

  Data Path: clockkernel_screen_FFd1 to N<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           13   0.619   0.895  clockkernel_screen_FFd1 (clockkernel_screen_FFd1)
     LUT2:I1->O           13   0.720   0.895  clockkernel__n00931 (clockkernel__COND_3<2>)