clocktop.syr

一个在Xilinx spartan3实现的时钟

  4-bit up counter                 : 9
# Multiplexers                     : 3
  4-bit 16-to-1 multiplexer        : 1
  2-to-1 multiplexer               : 2
# Decoders                         : 1
  1-of-4 decoder                   : 1
# Adders/Subtractors               : 5
  4-bit adder                      : 5
# Comparators                      : 4
  4-bit comparator equal           : 2
  4-bit comparator not equal       : 2
# Xors                             : 2
  1-bit xor2                       : 1
  1-bit xor3                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <screen> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <clocktop> ...

Optimizing unit <noshake> ...

Optimizing unit <clockcore> ...
Loading device for application Xst from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clocktop, actual ratio is 4.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : clocktop.ngr
Top Level Output File Name         : clocktop
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 17

Macro Statistics :
# ROMs                             : 1
#      16x1-bit ROM                : 1
# Registers                        : 40
#      1-bit register              : 29
#      11-bit register             : 10
#      4-bit register              : 1
# Counters                         : 2
#      21-bit up counter           : 1
#      26-bit up counter           : 1
# Multiplexers                     : 3
#      2-to-1 multiplexer          : 2
#      4-bit 16-to-1 multiplexer   : 1
# Adders/Subtractors               : 10
#      11-bit adder                : 10
# Comparators                      : 4
#      4-bit comparator equal      : 2
#      4-bit comparator not equal  : 2
# Xors                             : 1
#      1-bit xor3                  : 1

Cell Usage :
# BELS                             : 415
#      GND                         : 1
#      LUT1                        : 21
#      LUT2                        : 32
#      LUT2_L                      : 23
#      LUT3                        : 66
#      LUT3_L                      : 1
#      LUT4                        : 95
#      LUT4_D                      : 7
#      LUT4_L                      : 25
#      MUXCY                       : 57
#      MUXF5                       : 17
#      MUXF6                       : 8
#      MUXF7                       : 4
#      VCC                         : 1
#      XORCY                       : 57
# FlipFlops/Latches                : 136
#      FDC                         : 21
#      FDC_1                       : 7
#      FDCE                        : 42
#      FDCPE                       : 47
#      FDP                         : 3
#      FDP_1                       : 2
#      FDPE                        : 14
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 16
#      IBUF                        : 4
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     149  out of   3584     4%  
 Number of Slice Flip Flops:           136  out of   7168     1%  
 Number of 4 input LUTs:               270  out of   7168     3%  
 Number of bonded IOBs:                 16  out of    141    11%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 60    |
shake_sample:Q                     | NONE                   | 3     |
clockkernel_sclkbuf(clockkernel_sclkbuf1:O)| NONE(*)(clockkernel_sec_0_2)| 9     |
clockkernel_y1buf(clockkernel_y1buf1:O)| NONE(*)(clockkernel_year_0_0)| 5     |
clockkernel_moncbuf(clockkernel_moncbuf1:O)| NONE(*)(clockkernel_month_0_0)| 9     |
clockkernel_daycbuf(clockkernel_daycbuf1:O)| NONE(*)(clockkernel_day_0_3)| 9     |
clockkernel_hclkbuf(clockkernel_hclkbuf1:O)| NONE(*)(clockkernel_hour_1_2)| 9     |
clockkernel_mclkbuf(clockkernel_mclkbuf1:O)| NONE(*)(clockkernel_min_1_3)| 9     |
clockkernel_y2buf(clockkernel_y2buf1:O)| NONE(*)(clockkernel_year3c)| 5     |
clockkernel_y3buf(clockkernel_y3buf1:O)| NONE(*)(clockkernel_year_2_3)| 5     |
clockkernel_y4buf(clockkernel_y4buf1:O)| NONE(*)(clockkernel_year_3_1)| 4     |
shake_noshakeb3:Q                  | NONE                   | 5     |
shake_noshakeb4:Q                  | NONE                   | 4     |
-----------------------------------+------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 8.948ns (Maximum Frequency: 111.751MHz)
   Minimum input arrival time before clock: 3.291ns
   Maximum output required time after clock: 11.680ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               8.948ns (Levels of Logic = 15)
  Source:            clockkernel_divcounter_44 (FF)
  Destination:       clockkernel_divcounter_46 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clockkernel_divcounter_44 to clockkernel_divcounter_46
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   0.619   0.465  clockkernel_divcounter_44 (clockkernel_divcounter_44)
     LUT4:I0->O            1   0.720   0.240  clockkernel__n001040 (CHOICE412)
     LUT4:I1->O           16   0.720   0.995  clockkernel__n001068 (CHOICE421)
     LUT4_D:I3->O         12   0.720   0.865  clockkernel__n001082 (clockkernel__n0010)
     LUT2_L:I0->LO         1   0.720   0.000  clockkernel_divcounter_inst_lut3_681 (clockkernel_divcounter_inst_lut3_68)
     MUXCY:S->O            1   0.629   0.000  clockkernel_divcounter_inst_cy_49 (clockkernel_divcounter_inst_cy_49)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_50 (clockkernel_divcounter_inst_cy_50)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_51 (clockkernel_divcounter_inst_cy_51)
     MUXCY:CI->O           1   0.091   0.000  clockkernel_divcounter_inst_cy_52 (clockkernel_divcounter_inst_cy_52)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_53 (clockkernel_divcounter_inst_cy_53)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_54 (clockkernel_divcounter_inst_cy_54)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_55 (clockkernel_divcounter_inst_cy_55)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_56 (clockkernel_divcounter_inst_cy_56)
     MUXCY:CI->O           1   0.090   0.000  clockkernel_divcounter_inst_cy_57 (clockkernel_divcounter_inst_cy_57)
     MUXCY:CI->O           0   0.090   0.000  clockkernel_divcounter_inst_cy_58 (clockkernel_divcounter_inst_cy_58)
     XORCY:CI->O           1   0.939   0.000  clockkernel_divcounter_inst_sum_57 (clockkernel_divcounter_inst_sum_57)
     FDCPE:D                   0.502          clockkernel_divcounter_46
    ----------------------------------------
    Total                      8.948ns (6.383ns logic, 2.565ns route)
                                       (71.3% logic, 28.7% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_sclkbuf1:O'
Delay:               5.063ns (Levels of Logic = 3)
  Source:            clockkernel_sec_0_0 (FF)
  Destination:       clockkernel_mclk (FF)
  Source Clock:      clockkernel_sclkbuf1:O rising
  Destination Clock: clockkernel_sclkbuf1:O rising

  Data Path: clockkernel_sec_0_0 to clockkernel_mclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             6   0.619   0.688  clockkernel_sec_0_0 (clockkernel_sec_0_0)
     LUT4:I2->O            4   0.720   0.629  clockkernel__n00131 (clockkernel__n0013)
     LUT4:I0->O            2   0.720   0.465  clockkernel__n0051 (clockkernel__n0051)
     LUT3:I2->O            1   0.720   0.000  clockkernel__n0012<2>1 (clockkernel__n0012<2>)
     FDCE:D                    0.502          clockkernel_sec_1_2
    ----------------------------------------
    Total                      5.063ns (3.281ns logic, 1.782ns route)
                                       (64.8% logic, 35.2% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clockkernel_y1buf1:O'
Delay:               3.459ns (Levels of Logic = 2)
  Source:            clockkernel_year_0_2 (FF)
  Destination:       clockkernel_year2c (FF)
  Source Clock:      clockkernel_y1buf1:O rising
  Destination Clock: clockkernel_y1buf1:O rising

  Data Path: clockkernel_year_0_2 to clockkernel_year2c
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             5   0.619   0.658  clockkernel_year_0_2 (clockkernel_year_0_2)
     LUT4:I3->O            1   0.720   0.240  clockkernel__n0151_SW0 (N12395)
     LUT4:I1->O            1   0.720   0.000  clockkernel__n0151 (clockkernel__n0151)
     FDC:D                     0.502          clockkernel_year2c
    ----------------------------------------
    Total                      3.459ns (2.561ns logic, 0.898ns route)
                                       (74.0% logic, 26.0% route)