📄 clockcore.mrp
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Release 6.1i Map G.23Xilinx Mapping Report File for Design 'clockcore'Design Information------------------Command Line : D:/Xilinx/bin/nt/map.exe -intstyle ise -p xc3s400-pq208-4 -cm
area -pr b -k 4 -c 100 -tx off -o clockcore_map.ncd clockcore.ngd clockcore.pcf Target Device : x3s400Target Package : pq208Target Speed : -4Mapper Version : spartan3 -- $Revision: 1.16 $Mapped Date : Tue Jul 31 21:56:54 2007Design Summary--------------Number of errors: 0Number of warnings: 11Logic Utilization: Total Number Slice Registers: 115 out of 7,168 1% Number used as Flip Flops: 111 Number used as Latches: 4 Number of 4 input LUTs: 192 out of 7,168 2%Logic Distribution: Number of occupied Slices: 112 out of 3,584 3% Number of Slices containing only related logic: 112 out of 112 100% Number of Slices containing unrelated logic: 0 out of 112 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 202 out of 7,168 2% Number used as logic: 192 Number used as a route-thru: 10 Number of bonded IOBs: 17 out of 141 12% Number of GCLKs: 3 out of 8 37%Total equivalent gate count for design: 2,378Additional JTAG gate count for IOBs: 816Peak Memory Usage: 75 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net daycbuf is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:367 - Netcheck: Loadless. Net day_0__n0001<3> has no load.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y2buf is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y3buf is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y4buf is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hclkbuf is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0144 is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net sclkbuf is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net mclkbuf is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net moncbuf is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y1buf is sourced by a
combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.Section 3 - Informational-------------------------INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "b3_BUFGP" (output signal=b3_BUFGP), BUFGP symbol "b4_BUFGP" (output signal=b4_BUFGP), BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| N<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || N<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || P<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || b1 | IOB | INPUT | LVCMOS25 | | | | | || b2 | IOB | INPUT | LVCMOS25 | | | | | || b3 | IOB | INPUT | LVCMOS25 | | | | | || b4 | IOB | INPUT | LVCMOS25 | | | | | || clk | IOB | INPUT | LVCMOS25 | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.⌨️ 快捷键说明
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