📄 ss_smii_tomii_top.vhd
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------------------------------------------------------------------------------
-- --
-- SMII To MII Module Design --
-- --
-- Copyright (C) Level One Communications --
-- an intel company --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- FILE NAME : SS_SMII_TOMII.VHD --
-- FUNCTION : THIS MODULE CONVERTS MII TO SMII & SMII TO MII --
-- AUTHOR : PETE RAMOS --
-- DATE : May 2000 --
------------------------------------------------------------------------------
-- Notes:
--
--
--
--
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY SS_SMII_TOMII_TOP IS
PORT(
--
-- BOARD RESET & STATUS LED'S
--
nRESET :in std_logic; -- ACTIVE LOW
SYNC_FPGA_A :out std_logic;
SYNC_FPGA_B :in std_logic;
PORT_STATUS_P0 :out std_logic_vector(6 downto 0);
PORT_STATUS_P1 :out std_logic_vector(6 downto 0);
PORT_STATUS_P2 :out std_logic_vector(6 downto 0);
PORT_STATUS_P3 :out std_logic_vector(6 downto 0);
-- 7='1'
-- 6=FALSE CARRIER DETECT,
-- 5=UPPER NIBBLE VALID(0=INVALID, 1=VALID),
-- 4=JABBER(0=OK, 1=ERROR),
-- 3=LINK(0=DOWN, 1=UP),
-- 2=DUPLEX(0=HALF, 1=FULL),
-- 1=SPEED(0=10Mbps, 1=100Mbps),
-- 0=RX_ER FROM PREVIOUS FRAME
--
SW_OVERRIDE :in std_logic_vector(2 downto 0);
-- 2=DUPLEX(HALF('0'), FULL('1'))
-- 1=SPEED(10('0'), 100(1)
-- 0=AUTO('0')/MANUAL OVERRIDE('1')
--
-- SMII SIGNALS
--
SMII_REFCLK :in std_logic; -- 125 MHz CLOCK
SMII_SYNC :out std_logic;
--
-- (RX)
--
SMII_RXD_P0 :in std_logic;
--
SMII_RXD_P1 :in std_logic;
--
SMII_RXD_P2 :in std_logic;
--
SMII_RXD_P3 :in std_logic;
--
-- (TX)
--
SMII_TXD_P0 :out std_logic;
--
SMII_TXD_P1 :out std_logic;
--
SMII_TXD_P2 :out std_logic;
--
SMII_TXD_P3 :out std_logic;
--
-- MII SIGNALS
--
MII_CRS_P0 :out std_logic;
MII_COL_P0 :out std_logic;
--
MII_CRS_P1 :out std_logic;
MII_COL_P1 :out std_logic;
--
MII_CRS_P2 :out std_logic;
MII_COL_P2 :out std_logic;
--
MII_CRS_P3 :out std_logic;
MII_COL_P3 :out std_logic;
--
-- (RX)
MII_RXCLK_P0 :out std_logic; -- mii clock which is also provided to the MII port
MII_RXER_P0 :out std_logic;
MII_RXDV_P0 :out std_logic;
MII_RXD0_P0 :out std_logic;
MII_RXD1_P0 :out std_logic;
MII_RXD2_P0 :out std_logic;
MII_RXD3_P0 :out std_logic;
--
MII_RXCLK_P1 :out std_logic; -- mii clock which is also provided to the MII port
MII_RXER_P1 :out std_logic;
MII_RXDV_P1 :out std_logic;
MII_RXD0_P1 :out std_logic;
MII_RXD1_P1 :out std_logic;
MII_RXD2_P1 :out std_logic;
MII_RXD3_P1 :out std_logic;
--
MII_RXCLK_P2 :out std_logic; -- mii clock which is also provided to the MII port
MII_RXER_P2 :out std_logic;
MII_RXDV_P2 :out std_logic;
MII_RXD0_P2 :out std_logic;
MII_RXD1_P2 :out std_logic;
MII_RXD2_P2 :out std_logic;
MII_RXD3_P2 :out std_logic;
--
MII_RXCLK_P3 :out std_logic; -- mii clock which is also provided to the MII port
MII_RXER_P3 :out std_logic;
MII_RXDV_P3 :out std_logic;
MII_RXD0_P3 :out std_logic;
MII_RXD1_P3 :out std_logic;
MII_RXD2_P3 :out std_logic;
MII_RXD3_P3 :out std_logic;
--
-- (TX)
MII_TXCLK_P0 :out std_logic; -- mii clock which is also provided to the MII port
MII_TXER_P0 :in std_logic;
MII_TXEN_P0 :in std_logic;
MII_TXD0_P0 :in std_logic;
MII_TXD1_P0 :in std_logic;
MII_TXD2_P0 :in std_logic;
MII_TXD3_P0 :in std_logic;
--
MII_TXCLK_P1 :out std_logic; -- mii clock which is also provided to the MII port
MII_TXER_P1 :in std_logic;
MII_TXEN_P1 :in std_logic;
MII_TXD0_P1 :in std_logic;
MII_TXD1_P1 :in std_logic;
MII_TXD2_P1 :in std_logic;
MII_TXD3_P1 :in std_logic;
--
MII_TXCLK_P2 :out std_logic; -- mii clock which is also provided to the MII port
MII_TXER_P2 :in std_logic;
MII_TXEN_P2 :in std_logic;
MII_TXD0_P2 :in std_logic;
MII_TXD1_P2 :in std_logic;
MII_TXD2_P2 :in std_logic;
MII_TXD3_P2 :in std_logic;
--
MII_TXCLK_P3 :out std_logic; -- mii clock which is also provided to the MII port
MII_TXER_P3 :in std_logic;
MII_TXEN_P3 :in std_logic;
MII_TXD0_P3 :in std_logic;
MII_TXD1_P3 :in std_logic;
MII_TXD2_P3 :in std_logic;
MII_TXD3_P3 :in std_logic);
END SS_SMII_TOMII_TOP;
ARCHITECTURE SS_SMII_LOGIC Of SS_SMII_TOMII_TOP IS
signal iSMII_SYNC_P1 :std_logic;
signal iSMII_SYNC_P2 :std_logic;
signal iSMII_SYNC_P3 :std_logic;
signal iSYNC_FPGA_A_P1 :std_logic;
signal iSYNC_FPGA_A_P2 :std_logic;
signal iSYNC_FPGA_A_P3 :std_logic;
COMPONENT SS_SMII_TOMII
PORT(
nRESET :in std_logic; -- ACTIVE LOW
SYNC_FPGA_A :out std_logic;
SYNC_FPGA_B :in std_logic;
PORT_STATUS :out std_logic_vector(6 downto 0);
SW_OVERRIDE :in std_logic_vector(2 downto 0);
--
-- SMII SIGNALS
--
SMII_REFCLK0 :in std_logic; -- 125 MHz CLOCK
SMII_REFCLK1 :in std_logic; -- 125 MHz CLOCK
SMII_SYNC :out std_logic;
--
-- (RX)
SMII_RXD :in std_logic;
-- (TX)
SMII_TXD :out std_logic;
--
-- MII SIGNALS
--
MII_CRS :out std_logic;
MII_COL :out std_logic;
-- (RX)
MII_RXCLK :out std_logic; -- mii clock which is also provided to the MII port
MII_RXER :out std_logic;
MII_RXDV :out std_logic;
MII_RXD0 :out std_logic;
MII_RXD1 :out std_logic;
MII_RXD2 :out std_logic;
MII_RXD3 :out std_logic;
-- (TX)
MII_TXCLK :out std_logic; -- mii clock which is also provided to the MII port
MII_TXER :in std_logic;
MII_TXEN :in std_logic;
MII_TXD0 :in std_logic;
MII_TXD1 :in std_logic;
MII_TXD2 :in std_logic;
MII_TXD3 :in std_logic);
END COMPONENT;
BEGIN
U0: SS_SMII_TOMII PORT MAP(nRESET=>nRESET, SYNC_FPGA_A=>SYNC_FPGA_A, SYNC_FPGA_B=>SYNC_FPGA_B, PORT_STATUS=>PORT_STATUS_P0, SW_OVERRIDE=>SW_OVERRIDE,
SMII_REFCLK0=>SMII_REFCLK, SMII_REFCLK1=>SMII_REFCLK, SMII_SYNC=>iSMII_SYNC_P1, SMII_RXD=>SMII_RXD_P0, SMII_TXD=>SMII_TXD_P0, MII_CRS=>MII_CRS_P0, MII_COL=>MII_COL_P0,
MII_RXCLK=>MII_RXCLK_P0, MII_RXER=>MII_RXER_P0, MII_RXDV=>MII_RXDV_P0, MII_RXD0=>MII_RXD0_P0, MII_RXD1=>MII_RXD1_P0, MII_RXD2=>MII_RXD2_P0,
MII_RXD3=>MII_RXD3_P0, MII_TXCLK=>MII_TXCLK_P0, MII_TXER=>MII_TXER_P0, MII_TXEN=>MII_TXEN_P0, MII_TXD0=>MII_TXD0_P0, MII_TXD1=>MII_TXD1_P0,
MII_TXD2=>MII_TXD2_P0, MII_TXD3=>MII_TXD3_P0);
U1: SS_SMII_TOMII PORT MAP(nRESET=>nRESET, SYNC_FPGA_A=>iSYNC_FPGA_A_P1, SYNC_FPGA_B=>SYNC_FPGA_B, PORT_STATUS=>PORT_STATUS_P1, SW_OVERRIDE=>SW_OVERRIDE,
SMII_REFCLK0=>SMII_REFCLK, SMII_REFCLK1=>SMII_REFCLK, SMII_SYNC=>SMII_SYNC, SMII_RXD=>SMII_RXD_P1, SMII_TXD=>SMII_TXD_P1, MII_CRS=>MII_CRS_P1, MII_COL=>MII_COL_P1,
MII_RXCLK=>MII_RXCLK_P1, MII_RXER=>MII_RXER_P1, MII_RXDV=>MII_RXDV_P1, MII_RXD0=>MII_RXD0_P1, MII_RXD1=>MII_RXD1_P1, MII_RXD2=>MII_RXD2_P1,
MII_RXD3=>MII_RXD3_P1, MII_TXCLK=>MII_TXCLK_P1, MII_TXER=>MII_TXER_P1, MII_TXEN=>MII_TXEN_P1, MII_TXD0=>MII_TXD0_P1, MII_TXD1=>MII_TXD1_P1,
MII_TXD2=>MII_TXD2_P1, MII_TXD3=>MII_TXD3_P1);
U2: SS_SMII_TOMII PORT MAP(nRESET=>nRESET, SYNC_FPGA_A=>iSYNC_FPGA_A_P2, SYNC_FPGA_B=>SYNC_FPGA_B, PORT_STATUS=>PORT_STATUS_P2, SW_OVERRIDE=>SW_OVERRIDE,
SMII_REFCLK0=>SMII_REFCLK, SMII_REFCLK1=>SMII_REFCLK, SMII_SYNC=>iSMII_SYNC_P2, SMII_RXD=>SMII_RXD_P2, SMII_TXD=>SMII_TXD_P2, MII_CRS=>MII_CRS_P2, MII_COL=>MII_COL_P2,
MII_RXCLK=>MII_RXCLK_P2, MII_RXER=>MII_RXER_P2, MII_RXDV=>MII_RXDV_P2, MII_RXD0=>MII_RXD0_P2, MII_RXD1=>MII_RXD1_P2, MII_RXD2=>MII_RXD2_P2,
MII_RXD3=>MII_RXD3_P2, MII_TXCLK=>MII_TXCLK_P2, MII_TXER=>MII_TXER_P2, MII_TXEN=>MII_TXEN_P2, MII_TXD0=>MII_TXD0_P2, MII_TXD1=>MII_TXD1_P2,
MII_TXD2=>MII_TXD2_P2, MII_TXD3=>MII_TXD3_P2);
U3: SS_SMII_TOMII PORT MAP(nRESET=>nRESET, SYNC_FPGA_A=>iSYNC_FPGA_A_P3, SYNC_FPGA_B=>SYNC_FPGA_B, PORT_STATUS=>PORT_STATUS_P3, SW_OVERRIDE=>SW_OVERRIDE,
SMII_REFCLK0=>SMII_REFCLK, SMII_REFCLK1=>SMII_REFCLK, SMII_SYNC=>iSMII_SYNC_P3, SMII_RXD=>SMII_RXD_P3, SMII_TXD=>SMII_TXD_P3, MII_CRS=>MII_CRS_P3, MII_COL=>MII_COL_P3,
MII_RXCLK=>MII_RXCLK_P3, MII_RXER=>MII_RXER_P3, MII_RXDV=>MII_RXDV_P3, MII_RXD0=>MII_RXD0_P3, MII_RXD1=>MII_RXD1_P3, MII_RXD2=>MII_RXD2_P3,
MII_RXD3=>MII_RXD3_P3, MII_TXCLK=>MII_TXCLK_P3, MII_TXER=>MII_TXER_P3, MII_TXEN=>MII_TXEN_P3, MII_TXD0=>MII_TXD0_P3, MII_TXD1=>MII_TXD1_P3,
MII_TXD2=>MII_TXD2_P3, MII_TXD3=>MII_TXD3_P3);
END SS_SMII_LOGIC;
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