ss_smii_tomii.vhd

SMII 到 MII 转换的VHDL代码

				MII_COL<='0';
			end if;
		when others=>
		end case;
	End Process;
--
--	RX
--
	Process(nRESET, iMII_RXCLK)
	Begin
		if(nRESET='0')then
			iMII_CNT0<='1';
		elsif(iMII_RXCLK'EVENT and iMII_RXCLK='0')then
			iMII_CNT0<=not iMII_CNT0;
		end if;
	End Process;
	Process(iMII_RXCLK)
	Begin
		if(iMII_RXCLK'EVENT and iMII_RXCLK='1')then
----------- load data a 1/2 cycle before clocking it out
			if(iMII_CNT0='1')then
--------------- data valid					
				if(iSMII_RXDV_0(2)='1')then
------------------- false carrier detected
					if(iLSTFRM_FALSECRS_0(1)='1')then
						iMII_RXDV<="00";
						iMII_RXER<="01";
						iMII_RXD0<="00";
						iMII_RXD1<="01";
						iMII_RXD2<="01";
						iMII_RXD3<="01";
------------------- upper nibble invalid												
					elsif(iLSTFRM_UPNIBVAL_0(1)='0')then
						iMII_RXDV<="01";		
						iMII_RXER<='0' & iLSTFRM_RXER_0(1);							
						iMII_RXD0<='0' & iSMII_RXD_2(0);
						iMII_RXD1<='0' & iSMII_RXD_2(1);
						iMII_RXD2<='0' & iSMII_RXD_2(2);
						iMII_RXD3<='0' & iSMII_RXD_2(3);
------------------- no false carrier detected and upper nibble valid
					else
						iMII_RXDV<="11";							
						iMII_RXER<=iLSTFRM_RXER_0(1) & iLSTFRM_RXER_0(1);							
						iMII_RXD0<=iSMII_RXD_2(4) & iSMII_RXD_2(0);
						iMII_RXD1<=iSMII_RXD_2(5) & iSMII_RXD_2(1);
						iMII_RXD2<=iSMII_RXD_2(6) & iSMII_RXD_2(2);
						iMII_RXD3<=iSMII_RXD_2(7) & iSMII_RXD_2(3);
					end if;
--------------- data not valid						
				else
------------------- false carrier detected
					if(iLSTFRM_FALSECRS_0(1)='1')then
						iMII_RXDV<="00";							
						iMII_RXER<="01";
						iMII_RXD0<="00";
						iMII_RXD1<="01";
						iMII_RXD2<="01";
						iMII_RXD3<="01";								
------------------- no false carrier(idle state)						
					else
						iMII_RXDV<="00";							
						iMII_RXER<="00";
						iMII_RXD0<="00";
						iMII_RXD1<="00";
						iMII_RXD2<="00";
						iMII_RXD3<="00";
					end if;	
				end if;	
----------- shift data 1/2 cycle before output flip flop
			else
				iMII_RXDV<='0' & iMII_RXDV(1);
				iMII_RXER<='0' & iMII_RXER(1);
				iMII_RXD0<='0' & iMII_RXD0(1);
				iMII_RXD1<='0' & iMII_RXD1(1);
				iMII_RXD2<='0' & iMII_RXD2(1);
				iMII_RXD3<='0' & iMII_RXD3(1);
			end if;
		end if;
	End Process;
--	re-clock data out to decrease output to clock skew(output delay)
	Process(iMII_RXCLK)
	Begin
		if(iMII_RXCLK'EVENT and iMII_RXCLK='0')then
			MII_RXDV<=iMII_RXDV(0);
			iMII_RXDV_0<=iMII_RXDV(0);
			MII_RXD0<=iMII_RXD0(0);
			MII_RXD1<=iMII_RXD1(0);
			MII_RXD2<=iMII_RXD2(0);
			MII_RXD3<=iMII_RXD3(0);
			MII_RXER<=iMII_RXER(0);
		end if;
	End Process;
--
--	TX
--
	Process(iMII_TXCLK)
	Begin
		if(iMII_TXCLK'EVENT and iMII_TXCLK='1')then
			if(MII_TXEN='1')then
				iMII_TXCNT<=not iMII_TXCNT;				
				iNEW_MIITX<='1';
			else
				iNEW_MIITX<='0';
				iMII_TXCNT<='0';
			end if;
		end if;
	End Process;
	Process(iMII_TXCLK)
	Begin
		if(iMII_TXCLK'EVENT and iMII_TXCLK='1')then
			if(MII_TXEN='1')then
				if(iMII_TXCNT='1')then
					iMII_TXD<=MII_TXD3 & MII_TXD2 & MII_TXD1 & MII_TXD0 & iMII_TXD(3 downto 0);				
				else
					iMII_TXD<=iMII_TXD(7 downto 4) & MII_TXD3 & MII_TXD2 & MII_TXD1 & MII_TXD0;				
					iMII_TXEN<=MII_TXEN;
					iMII_TXER<=MII_TXER;
				end if;
			else
				if(iNEW_MIITX='0')then
					iMII_TXD<="00000000";
					iMII_TXEN<='0';
					iMII_TXER<='0';
				end if;
			end if;
		end if;
	End Process;
	Process(iMII_TXCLK)
	Begin
		if(iMII_TXCLK'EVENT and iMII_TXCLK='0')then
			if(iMII_TXCNT='0')then
				iMII_TXD_0<=iMII_TXD & iMII_TXEN & iMII_TXER;
			end if;
		end if;
	End Process;


-------------------------------------------------------------------------
--																		-
--								SMII									-
--																		-
-------------------------------------------------------------------------
--
--	RX
--
	Process(SMII_REFCLK1)
	Begin
		if(SMII_REFCLK1'EVENT and SMII_REFCLK1='1')then
			if(iSMII_RXCNT="0000")then		    
				if(iSPEED='0')then
					if(iSMII_SYCNT="1001" or SHFTLSTDAT_CNT="100")then
						iSMII_SYCNT<="0000";
					else
						iSMII_SYCNT<=iSMII_SYCNT+1;
					end if;
					if(iSMII_RXDV='0')then
						if(iSMII_SYCNT="1001" and SHFTLSTDAT_CNT/="100")then
							SHFTLSTDAT_CNT<=SHFTLSTDAT_CNT+1;
						end if;
					else
						SHFTLSTDAT_CNT<="000";
					end if;
				else
					SHFTLSTDAT_CNT<="000";
					iSMII_SYCNT<="0001";
				end if;
			end if;
		end if;
	End Process;
	
	Process(SMII_REFCLK1)
	Begin
		if(SMII_REFCLK1'EVENT and SMII_REFCLK1='1')then
			if(iSMII_SYNC='1')then
				iSMII_RXCNT<="0000";
			else
				iSMII_RXCNT<=iSMII_RXCNT+1;
			end if;
		end if;
	End Process;
	Process(SMII_REFCLK1)
	Begin
		if(SMII_REFCLK1'EVENT and SMII_REFCLK1='1')then
			if(iSMII_RXCNT="0010" and iSMII_SYCNT="0001")then
				iSMII_RXCRS_0<=iSMII_RXCRS_0(2 downto 0) & iSMII_RXCRS;
				iLSTFRM_RXER_0<=iLSTFRM_RXER_0(0) & iLSTFRM_RXER;
				iLSTFRM_UPNIBVAL_0<=iLSTFRM_UPNIBVAL_0(1 downto 0) & iLSTFRM_UPNIBVAL;
				iLSTFRM_FALSECRS_0<=iLSTFRM_FALSECRS_0(1 downto 0) & iLSTFRM_FALSECRS;
				iSPEED_0<=iSPEED;
				iDUPLEX_0<=iDUPLEX;
				iSMII_RXDV_0<=iSMII_RXDV_0(2 downto 0) & iSMII_RXDV0;
				iSMII_RXD_0<=iSMII_RXD;
				iSMII_RXD_1<=iSMII_RXD_0;
				iSMII_RXD_2<=iSMII_RXD_1;
			end if;
		end if;
	End Process;
	Process(SMII_REFCLK1)
	Begin
		if(SMII_REFCLK1'EVENT and SMII_REFCLK1='1')then
			if(iSMII_RXCNT="0000")then
				iSMII_RXCRS<=SMII_RXD;
				iSMII_RXDV0<=iSMII_RXDV;
				if(iSMII_RXDV='0')then
					iLSTFRM_RXER<=iSMII_RXD(0);
					iLSTFRM_UPNIBVAL<=iSMII_RXD(5);
					iLSTFRM_FALSECRS<=iSMII_RXD(6);
					PORT_STATUS<=iSMII_RXD(6 downto 0);
					iDUPLEX<=iSMII_RXD(2);
					iSPEED<=iSMII_RXD(1);
				else
					iLSTFRM_RXER<='0';
					iLSTFRM_UPNIBVAL<='1';
					iLSTFRM_FALSECRS<='0';
				end if;
			elsif(iSMII_RXCNT="0001")then
				iSMII_RXDV<=SMII_RXD;
			else
				iSMII_RXD<=SMII_RXD & iSMII_RXD(7 downto 1);
			end if;
		end if;
	End Process;

--
--	TX
--
--  logic to sync txsync on both fpga's 	
	Process(SMII_REFCLK0)
	Begin
		if(SMII_REFCLK0'EVENT AND SMII_REFCLK0='1') then
			case SYNC_STATE is
				when st0=>	
--					iSTART_TXSYNC<='0';
					SYNC_FPGA_A<='0';										
					if(iSYNC_FPGA_CNT0="111")then
						NEXT_STATE<=st1;
					else
						iSYNC_FPGA_CNT0<=iSYNC_FPGA_CNT0+1;					
						NEXT_STATE<=st0;
					end if;
				when st1=>	
					SYNC_FPGA_A<='1';
--					if(SYNC_FPGA_B='1')then
--						iSTART_TXSYNC<='0';									
--					end if;
					NEXT_STATE<=st2;					
				when st2=>		
					SYNC_FPGA_A<='1';				
--					if(SYNC_FPGA_B='1')then
--						iSTART_TXSYNC<='1';									
--					end if;
					NEXT_STATE<=st3;								
				when st3=>		
					SYNC_FPGA_A<='1';				
--					if(SYNC_FPGA_B='1')then
--						iSTART_TXSYNC<='1';									
--					end if;
					NEXT_STATE<=st3;								
				when others=>
					NEXT_STATE<=st0;
			end case;
		end if;
	End Process;
	SYNC_STATE<=NEXT_STATE;	
	Process(SMII_REFCLK0)
	Begin
		if(SMII_REFCLK0'EVENT AND SMII_REFCLK0='0') then
			case SYNC_STATE is
				when st0=>	
					iSTART_TXSYNC<='0';
				when st1=>	
					iSTART_TXSYNC<='0';									
				when st2=>		
					iSTART_TXSYNC<='0';									
				when st3=>
					if(SYNC_FPGA_B='1')then
						iSTART_TXSYNC<='1';									
					end if;
				when others=>
					iSTART_TXSYNC<='0';
			end case;
		end if;
	End Process;

--  create tx sync	
	Process(SMII_REFCLK0)
	Begin
		if(SMII_REFCLK0'EVENT and SMII_REFCLK0='0')then
			if(iSTART_TXSYNC='1')then
				if(iSYNC_CNT="1001")then
					iSYNC_CNT<="0000";
					SMII_SYNC<='1';
					iSMII_SYNC<='1';
				else
					iSYNC_CNT<=iSYNC_CNT+1;
					SMII_SYNC<='0';
					iSMII_SYNC<='0';
				end if;					
			end if;
		end if;
	End Process;
	Process(SMII_REFCLK0)
	Begin
		if(SMII_REFCLK0'EVENT and SMII_REFCLK0='0')then
			if(iSYNC_CNT="1000")then
				iSMII_TXD<=iMII_TXD_0;
			else
				iSMII_TXD<='0' & iSMII_TXD(9 downto 1);
			end if;
		end if;
	End Process;
	Process(SMII_REFCLK0)
	Begin
		if(SMII_REFCLK0'EVENT and SMII_REFCLK0='0')then
			SMII_TXD<=iSMII_TXD(0);
		end if;
	End Process;

END SS_SMII_LOGIC;