📄 ss_smii_tomii.vhd
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------------------------------------------------------------------------------
-- --
-- SMII To MII Module Design --
-- --
-- Copyright (C) Level One Communications --
-- an intel company --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- FILE NAME : SMII_TOMII.VHD --
-- FUNCTION : THIS MODULE CONVERTS MII TO SMII & SMII TO MII --
-- AUTHOR : PETE RAMOS --
-- DATE : May 2000 --
------------------------------------------------------------------------------
-- Notes:
--
-- 1. For this module to work properly the SMII_SYNC and the MII_CLK
-- rising edge must be in phase with each other.
--
--
--
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY SS_SMII_TOMII IS
PORT(
--
-- BOARD RESET & STATUS LED'S
--
nRESET :in std_logic; -- ACTIVE LOW
SYNC_FPGA_A :out std_logic;
SYNC_FPGA_B :in std_logic;
PORT_STATUS :out std_logic_vector(6 downto 0);
-- 7='1'
-- 6=FALSE CARRIER DETECT,
-- 5=UPPER NIBBLE VALID(0=INVALID, 1=VALID),
-- 4=JABBER(0=OK, 1=ERROR),
-- 3=LINK(0=DOWN, 1=UP),
-- 2=DUPLEX(0=HALF, 1=FULL),
-- 1=SPEED(0=10Mbps, 1=100Mbps),
-- 0=RX_ER FROM PREVIOUS FRAME
--
SW_OVERRIDE :in std_logic_vector(2 downto 0);
-- 2=DUPLEX(HALF('0'), FULL('1'))
-- 1=SPEED(10('0'), 100(1)
-- 0=AUTO('0')/MANUAL OVERRIDE('1')
--
-- SMII SIGNALS
--
-- DEBUG SIGNALS
-- SMII_SYCNT :out std_logic_vector(3 downto 0);
-- SMII_RXCNT :out std_logic_vector(3 downto 0);
-- SMII_CRS :out std_logic_vector(3 downto 0);
-- SMII_DV :out std_logic_vector(3 downto 0);
-- FALSECRS :out std_logic_vector(2 downto 0);
-- UPNIBVAL :out std_logic_vector(2 downto 0);
-- SPEED :out std_logic;
-- RMII_DV :out std_logic_vector(3 downto 0);
-- RMII_CRS :out std_logic_vector(3 downto 0);
-- RMII_CNT0 :out std_logic_vector(1 downto 0);
-- RMII_CNT1 :out std_logic_vector(3 downto 0);
-- DIBIT_CNT :out std_logic_vector(1 downto 0);
--
SMII_REFCLK0 :in std_logic; -- 125 MHz CLOCK
SMII_REFCLK1 :in std_logic; -- 125 MHz CLOCK
SMII_SYNC :out std_logic;
-- (RX)
SMII_RXD :in std_logic;
-- (TX)
SMII_TXD :out std_logic;
--
-- MII SIGNALS
--
MII_CRS :out std_logic;
MII_COL :out std_logic;
-- (RX)
MII_RXCLK :out std_logic; -- mii clock which is also provided to the MII port
MII_RXER :out std_logic;
MII_RXDV :out std_logic;
MII_RXD0 :out std_logic;
MII_RXD1 :out std_logic;
MII_RXD2 :out std_logic;
MII_RXD3 :out std_logic;
-- (TX)
MII_TXCLK :out std_logic; -- mii clock which is also provided to the MII port
MII_TXER :in std_logic;
MII_TXEN :in std_logic;
MII_TXD0 :in std_logic;
MII_TXD1 :in std_logic;
MII_TXD2 :in std_logic;
MII_TXD3 :in std_logic);
END SS_SMII_TOMII;
ARCHITECTURE SS_SMII_LOGIC Of SS_SMII_TOMII IS
type STATE_TYPE1 is(st0, st1, st2, st3);
signal SYNC_STATE :state_type1;
signal NEXT_STATE :state_type1;
signal iSTART_TXSYNC :std_logic;
-- IF SPEED=1 THEN 100Mbps ELSE 10Mbps
signal iSPEED :std_logic;
signal iSPEED_0 :std_logic;
signal iSPEED_1 :std_logic;
-- IF DUPLEX=1 THEN 100Mbps ELSE 10Mbps
signal iDUPLEX :std_logic;
signal iDUPLEX_0 :std_logic;
signal iDUPLEX_1 :std_logic;
-- USED TO DIVIDE SS_SMII_RXCLK TO MII_RXCLK
signal iSYNC_RXCLK :std_logic_vector(1 downto 0);
signal iDIV_RX100CLK :std_logic_vector(2 downto 0);
signal iMII_RX100CLK :std_logic;
signal iDIV_RX10CLK :std_logic_vector(3 downto 0);
signal iMII_RX10CLK :std_logic;
signal iMII_RXCLK :std_logic;
-- USED TO DIVIDE SMII_REFCLK TO MII TXCLK & RXCLK
signal iSYNC_TXCLK :std_logic_vector(1 downto 0);
signal iDIV_TX100CLK :std_logic_vector(2 downto 0);
signal iMII_TX100CLK :std_logic;
signal iDIV_TX10CLK :std_logic_vector(3 downto 0);
signal iMII_TX10CLK :std_logic;
signal iMII_TXCLK :std_logic;
--
-- MII
--
--
-- RX
signal iMII_CNT0 :std_logic;
signal iMII_RXDV :std_logic_vector(1 downto 0);
signal iMII_RXDV_0 :std_logic;
signal iMII_RXCRS :std_logic_vector(1 downto 0);
signal iMII_RXCRS_0 :std_logic;
signal iMII_RXER :std_logic_vector(1 downto 0);
signal iMII_RXD0 :std_logic_vector(1 downto 0);
signal iMII_RXD1 :std_logic_vector(1 downto 0);
signal iMII_RXD2 :std_logic_vector(1 downto 0);
signal iMII_RXD3 :std_logic_vector(1 downto 0);
signal iMII_RXCNT :std_logic_vector(1 downto 0);
signal iMII_LSTFRM_FALSECRS :std_logic;
signal iMII_LSTFRM_UPNIBVAL :std_logic;
signal iMII_LSTFRM_RXER :std_logic;
--
-- TX
signal iNEW_MIITX :std_logic;
signal iMII_TXCNT :std_logic;
signal iMII_TXD :std_logic_vector(7 downto 0);
signal iMII_TXD_0 :std_logic_vector(9 downto 0);
signal iMII_TXEN :std_logic;
signal iMII_TXEN_0 :std_logic;
signal iMII_TXER :std_logic;
signal iMII_TXER_0 :std_logic;
--
-- SMII
--
--
-- RX
signal SHFTLSTDAT_CNT :std_logic_vector(2 downto 0);
signal iSMII_SYCNT :std_logic_vector(3 downto 0);
signal iSMII_CNTH :std_logic_vector(3 downto 0);
signal iSMII_RXD :std_logic_vector(7 downto 0);
signal iSMII_RXD_0 :std_logic_vector(7 downto 0);
signal iSMII_RXD_1 :std_logic_vector(7 downto 0);
signal iSMII_RXD_2 :std_logic_vector(7 downto 0);
signal iSMII_RXCRS :std_logic;
signal iSMII_RXCRS_0 :std_logic_vector(3 downto 0);
signal iSMII_RXDV :std_logic;
signal iSMII_RXDV0 :std_logic;
signal iSMII_RXDV_0 :std_logic_vector(3 downto 0);
signal iSMII_RXCNT :std_logic_vector(3 downto 0);
-- last RX frame or upper nible status bits
signal iLSTFRM_FALSECRS :std_logic;
signal iLSTFRM_FALSECRS_0 :std_logic_vector(2 downto 0);
signal iLSTFRM_RXER :std_logic;
signal iLSTFRM_RXER_0 :std_logic_vector(1 downto 0);
signal iLSTFRM_UPNIBVAL :std_logic;
signal iLSTFRM_UPNIBVAL_0 :std_logic_vector(2 downto 0);
--
-- TX
signal iSYNC_FPGA_A :std_logic;
signal iSYNC_FPGA_CNT0 :std_logic_vector(2 downto 0);
signal iSYNC_CNT :std_logic_vector(3 downto 0);
signal iSMII_SYNC :std_logic;
signal iSMII_TXD :std_logic_vector(9 downto 0);
BEGIN
Process(SW_OVERRIDE)
Begin
case SW_OVERRIDE(0) is
when '0'=>
iSPEED_1<=iSPEED_0;
iDUPLEX_1<=iDUPLEX_0;
when '1'=>
iSPEED_1<=SW_OVERRIDE(1);
iDUPLEX_1<=SW_OVERRIDE(2);
when others=>
end case;
End Process;
--
-- creates mii rxclk for 25(100 Mbps) & 5(10 Mbps) MHz
--
Process(SMII_REFCLK1)
Begin
if(SMII_REFCLK1'EVENT and SMII_REFCLK1='1')then
if(iSMII_RXCNT="1001" and iSYNC_RXCLK/="11")then
iSYNC_RXCLK<=iSYNC_RXCLK+1;
elsif(iSYNC_RXCLK="11")then
if(iDIV_RX100CLK="100")then
iDIV_RX100CLK<="000";
else
iDIV_RX100CLK<=iDIV_RX100CLK+1;
end if;
if(iDIV_RX100CLK<"011")then
iMII_RX100CLK<='0';
else
iMII_RX100CLK<='1';
end if;
end if;
end if;
End Process;
Process(iMII_RX100CLK)
Begin
if(iMII_RX100CLK'EVENT and iMII_RX100CLK='1')then
if(iDIV_RX10CLK="1001")then
iDIV_RX10CLK<="0000";
else
iDIV_RX10CLK<=iDIV_RX10CLK+1;
end if;
if(iDIV_RX10CLK<"0101")then
iMII_RX10CLK<='0';
else
iMII_RX10CLK<='1';
end if;
end if;
End Process;
--
-- creates mii txclk for 25(100 Mbps) & 5(10 Mbps) MHz
--
Process(SMII_REFCLK0)
Begin
if(SMII_REFCLK0'EVENT and SMII_REFCLK0='1')then
if(iSYNC_CNT="1000" and iSYNC_TXCLK/="11")then
iSYNC_TXCLK<=iSYNC_TXCLK+1;
elsif(iSYNC_TXCLK="11")then
if(iDIV_TX100CLK="100")then
iDIV_TX100CLK<="000";
else
iDIV_TX100CLK<=iDIV_TX100CLK+1;
end if;
if(iDIV_TX100CLK<"011")then
iMII_TX100CLK<='0';
else
iMII_TX100CLK<='1';
end if;
end if;
end if;
End Process;
Process(iMII_TX100CLK)
Begin
if(iMII_TX100CLK'EVENT and iMII_TX100CLK='1')then
if(iDIV_TX10CLK="1001")then
iDIV_TX10CLK<="0000";
else
iDIV_TX10CLK<=iDIV_TX10CLK+1;
end if;
if(iDIV_TX10CLK<"0101")then
iMII_TX10CLK<='0';
else
iMII_TX10CLK<='1';
end if;
end if;
End Process;
Process(iSPEED_1)
Begin
case iSPEED_1 is
when '0'=>
iMII_RXCLK<=iMII_RX10CLK;
MII_RXCLK<=iMII_RX10CLK;
iMII_TXCLK<=iMII_TX10CLK;
MII_TXCLK<=iMII_TX10CLK;
when '1'=>
iMII_RXCLK<=iMII_RX100CLK;
MII_RXCLK<=iMII_RX100CLK;
iMII_TXCLK<=iMII_TX100CLK;
MII_TXCLK<=iMII_TX100CLK;
when others=>
end case;
End Process;
-------------------------------------------------------------------------
-- -
-- MII -
-- -
-------------------------------------------------------------------------
--
-- COMMON RX & TX MII SIGNALS
--
-- collission detect only when in half duplex
Process(iDUPLEX_1)
Begin
case iDUPLEX_1 is
when '1'=>
MII_COL<='0';
MII_CRS<='0';
when '0'=>
MII_CRS<=iSMII_RXCRS or MII_TXEN;
if(MII_TXEN='1' and iMII_RXDV_0='1')then
MII_COL<='1';
else
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