pwm.map.qmsg

来自「一个在CPLD」· QMSG 代码 · 共 13 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 07 20:52:30 2006 " "Info: Processing started: Fri Apr 07 20:52:30 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PWM -c pwm " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PWM -c pwm" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm-a " "Info: Found design unit 1: pwm-a" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm " "Info: Found entity 1: pwm" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pwm " "Info: Elaborating entity \"pwm\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "pwm_cnt\[0\] X pwm.vhd(20) " "Warning: Tied undriven net \"pwm_cnt\[0\]\" at pwm.vhd(20) to X" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 20 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "q\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"q\[0\]~0\"" {  } { { "pwm.vhd" "q\[0\]~0" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "diode\[0\] VCC " "Warning: Pin \"diode\[0\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "diode\[1\] VCC " "Warning: Pin \"diode\[1\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "diode\[2\] VCC " "Warning: Pin \"diode\[2\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "diode\[3\] VCC " "Warning: Pin \"diode\[3\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "diode\[4\] VCC " "Warning: Pin \"diode\[4\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 11 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[0\] VCC " "Warning: Pin \"led\[0\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[1\] VCC " "Warning: Pin \"led\[1\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[2\] VCC " "Warning: Pin \"led\[2\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[3\] VCC " "Warning: Pin \"led\[3\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[4\] VCC " "Warning: Pin \"led\[4\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[5\] VCC " "Warning: Pin \"led\[5\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[6\] VCC " "Warning: Pin \"led\[6\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[7\] VCC " "Warning: Pin \"led\[7\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 12 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cs\[0\] VCC " "Warning: Pin \"cs\[0\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cs\[1\] VCC " "Warning: Pin \"cs\[1\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cs\[2\] VCC " "Warning: Pin \"cs\[2\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 13 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cs\[3\] VCC " "Warning: Pin \"cs\[3\]\" stuck at VCC" {  } { { "pwm.vhd" "" { Text "H:/changzhou/edadiy/实验程序/PWM/pwm.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "62 " "Info: Implemented 62 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "38 " "Info: Implemented 38 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "3 " "Info: Implemented 3 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 07 20:52:37 2006 " "Info: Processing ended: Fri Apr 07 20:52:37 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}