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📄 up3_clock.map.rpt

📁 测试人体视觉的反应时间
💻 RPT
📖 第 1 页 / 共 4 页
字号:
; state.mode_set      ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1              ; 0                ; 0              ; 1            ;
; state.write_char1   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char2   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char3   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char4   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char5   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char6   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char7   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char8   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char9   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.write_char10  ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 1                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.return_home   ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 1                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.toggle_e      ; 0                   ; 0                 ; 0            ; 0            ; 0          ; 1              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.hold          ; 0                   ; 0                 ; 0            ; 0            ; 1          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.reset2        ; 0                   ; 0                 ; 0            ; 1            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.reset3        ; 0                   ; 0                 ; 1            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.display_off   ; 0                   ; 1                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
; state.display_clear ; 1                   ; 0                 ; 0            ; 0            ; 0          ; 0              ; 0                 ; 0                  ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0              ; 0                ; 0              ; 1            ;
+---------------------+---------------------+-------------------+--------------+--------------+------------+----------------+-------------------+--------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+----------------+------------------+----------------+--------------+


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; DATA_BUS_VALUE[6]                     ; Stuck at GND due to stuck port data_in ;
; LCD_RW~reg0                           ; Stuck at GND due to stuck port data_in ;
; next_command.toggle_e                 ; Stuck at GND due to stuck port data_in ;
; next_command.hold                     ; Stuck at GND due to stuck port data_in ;
; next_command.reset1                   ; Stuck at GND due to stuck port data_in ;
; BCD_SECD1[3]                          ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 6 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 155   ;
; Number of registers using Synchronous Clear  ; 63    ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 92    ;
; Number of registers using Asynchronous Load  ; 8     ;
; Number of registers using Clock Enable       ; 70    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; LCD_E~reg0                             ; 2       ;
; DATA_BUS_VALUE[3]                      ; 2       ;
; DATA_BUS_VALUE[4]                      ; 2       ;
; DATA_BUS_VALUE[5]                      ; 2       ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |UP3_CLOCK|COUNT[3]           ;
; 3:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |UP3_CLOCK|CLK_COUNT_400HZ[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Jul 23 11:34:55 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK
Info: Found 2 design units, including 1 entities, in source file UP3_CLOCK.vhd
    Info: Found design unit 1: UP3_CLOCK-a
    Info: Found entity 1: UP3_CLOCK
Info: Elaborating entity "UP3_CLOCK" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(59): signal "D1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(59): signal "K" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(244): signal "D1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(258): signal "K" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(341): signal "SW3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(359): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(359): signal "D1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(371): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(372): signal "D0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(372): signal "D4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(373): signal "CLK_400HZ" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (14130): Reduced register "DATA_BUS_VALUE[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "LCD_RW~reg0" with stuck data_in port to stuck value GND
Info: State machine "|UP3_CLOCK|next_command" contains 21 states
Info: State machine "|UP3_CLOCK|state" contains 21 states
Info: Selected Auto state machine encoding method for state machine "|UP3_CLOCK|next_command"
Info: Encoding result for state machine "|UP3_CLOCK|next_command"
    Info: Completed encoding using 21 state bits
        Info: Encoded state bit "next_command.display_clear"
        Info: Encoded state bit "next_command.display_off"
        Info: Encoded state bit "next_command.reset3"
        Info: Encoded state bit "next_command.hold"
        Info: Encoded state bit "next_command.reset1"
        Info: Encoded state bit "next_command.toggle_e"

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