📄 prev_cmp_up3_clock.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 23 11:16:22 2008 " "Info: Processing started: Wed Jul 23 11:16:22 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UP3_CLOCK -c UP3_CLOCK" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UP3_CLOCK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UP3_CLOCK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UP3_CLOCK-a " "Info: Found design unit 1: UP3_CLOCK-a" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 15 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 UP3_CLOCK " "Info: Found entity 1: UP3_CLOCK" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 7 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UP3_CLOCK " "Info: Elaborating entity \"UP3_CLOCK\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D1 UP3_CLOCK.vhd(59) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(59): signal \"D1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "K UP3_CLOCK.vhd(59) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(59): signal \"K\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D1 UP3_CLOCK.vhd(244) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(244): signal \"D1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "K UP3_CLOCK.vhd(258) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(258): signal \"K\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 258 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SW3 UP3_CLOCK.vhd(341) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(341): signal \"SW3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 341 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset UP3_CLOCK.vhd(359) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(359): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 359 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D1 UP3_CLOCK.vhd(359) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(359): signal \"D1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 359 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset UP3_CLOCK.vhd(371) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(371): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 371 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D0 UP3_CLOCK.vhd(372) " "Warning (10492): VHDL Process Statement warning at UP3_CLOCK.vhd(372): signal \"D0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 372 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
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