up3_clock.tan.qmsg

测试人体视觉的反应时间

{ "Info" "ITDB_TH_RESULT" "SEC_LED~reg0 D3 clk_48Mhz -0.760 ns register " "Info: th for register \"SEC_LED~reg0\" (data pin = \"D3\", clock pin = \"clk_48Mhz\") is -0.760 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 7.731 ns + Longest register " "Info: + Longest clock path from clock \"clk_48Mhz\" to destination register is 7.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns CLK_100HZ 2 REG LC_X26_Y10_N2 57 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X26_Y10_N2; Fanout = 57; REG Node = 'CLK_100HZ'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { clk_48Mhz CLK_100HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.854 ns) + CELL(0.711 ns) 7.731 ns SEC_LED~reg0 3 REG LC_X11_Y10_N7 2 " "Info: 3: + IC(3.854 ns) + CELL(0.711 ns) = 7.731 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'SEC_LED~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.565 ns" { CLK_100HZ SEC_LED~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.29 % ) " "Info: Total cell delay = 3.115 ns ( 40.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.616 ns ( 59.71 % ) " "Info: Total interconnect delay = 4.616 ns ( 59.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.731 ns" { clk_48Mhz CLK_100HZ SEC_LED~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.731 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} SEC_LED~reg0 {} } { 0.000ns 0.000ns 0.762ns 3.854ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.506 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.506 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D3 1 PIN PIN_49 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_49; Fanout = 6; PIN Node = 'D3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { D3 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.559 ns) + CELL(0.478 ns) 8.506 ns SEC_LED~reg0 2 REG LC_X11_Y10_N7 2 " "Info: 2: + IC(6.559 ns) + CELL(0.478 ns) = 8.506 ns; Loc. = LC_X11_Y10_N7; Fanout = 2; REG Node = 'SEC_LED~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.037 ns" { D3 SEC_LED~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 22.89 % ) " "Info: Total cell delay = 1.947 ns ( 22.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.559 ns ( 77.11 % ) " "Info: Total interconnect delay = 6.559 ns ( 77.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.506 ns" { D3 SEC_LED~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.506 ns" { D3 {} D3~out0 {} SEC_LED~reg0 {} } { 0.000ns 0.000ns 6.559ns } { 0.000ns 1.469ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.731 ns" { clk_48Mhz CLK_100HZ SEC_LED~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.731 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} SEC_LED~reg0 {} } { 0.000ns 0.000ns 0.762ns 3.854ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.506 ns" { D3 SEC_LED~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.506 ns" { D3 {} D3~out0 {} SEC_LED~reg0 {} } { 0.000ns 0.000ns 6.559ns } { 0.000ns 1.469ns 0.478ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 23 11:35:08 2008 " "Info: Processing ended: Wed Jul 23 11:35:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}