up3_clock.tan.qmsg

测试人体视觉的反应时间

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_100HZ " "Info: Detected ripple clock \"CLK_100HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_100HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_48Mhz register BCD_3CAI\[0\] register B2\[4\] 172.83 MHz 5.786 ns Internal " "Info: Clock \"clk_48Mhz\" has Internal fmax of 172.83 MHz between source register \"BCD_3CAI\[0\]\" and destination register \"B2\[4\]\" (period= 5.786 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.507 ns + Longest register register " "Info: + Longest register to register delay is 5.507 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_3CAI\[0\] 1 REG LC_X24_Y11_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y11_N9; Fanout = 6; REG Node = 'BCD_3CAI\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { BCD_3CAI[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.621 ns) + CELL(0.590 ns) 1.211 ns LessThan4~66 2 COMB LC_X24_Y11_N0 9 " "Info: 2: + IC(0.621 ns) + CELL(0.590 ns) = 1.211 ns; Loc. = LC_X24_Y11_N0; Fanout = 9; COMB Node = 'LessThan4~66'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.211 ns" { BCD_3CAI[0] LessThan4~66 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.389 ns) + CELL(0.292 ns) 3.892 ns B2\[7\]~516 3 COMB LC_X11_Y10_N5 7 " "Info: 3: + IC(2.389 ns) + CELL(0.292 ns) = 3.892 ns; Loc. = LC_X11_Y10_N5; Fanout = 7; COMB Node = 'B2\[7\]~516'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { LessThan4~66 B2[7]~516 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.748 ns) + CELL(0.867 ns) 5.507 ns B2\[4\] 4 REG LC_X12_Y10_N4 7 " "Info: 4: + IC(0.748 ns) + CELL(0.867 ns) = 5.507 ns; Loc. = LC_X12_Y10_N4; Fanout = 7; REG Node = 'B2\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.615 ns" { B2[7]~516 B2[4] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.749 ns ( 31.76 % ) " "Info: Total cell delay = 1.749 ns ( 31.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.758 ns ( 68.24 % ) " "Info: Total interconnect delay = 3.758 ns ( 68.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.507 ns" { BCD_3CAI[0] LessThan4~66 B2[7]~516 B2[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.507 ns" { BCD_3CAI[0] {} LessThan4~66 {} B2[7]~516 {} B2[4] {} } { 0.000ns 0.621ns 2.389ns 0.748ns } { 0.000ns 0.590ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.018 ns - Smallest " "Info: - Smallest clock skew is -0.018 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 7.731 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_48Mhz\" to destination register is 7.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns CLK_100HZ 2 REG LC_X26_Y10_N2 57 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X26_Y10_N2; Fanout = 57; REG Node = 'CLK_100HZ'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { clk_48Mhz CLK_100HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.854 ns) + CELL(0.711 ns) 7.731 ns B2\[4\] 3 REG LC_X12_Y10_N4 7 " "Info: 3: + IC(3.854 ns) + CELL(0.711 ns) = 7.731 ns; Loc. = LC_X12_Y10_N4; Fanout = 7; REG Node = 'B2\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.565 ns" { CLK_100HZ B2[4] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.29 % ) " "Info: Total cell delay = 3.115 ns ( 40.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.616 ns ( 59.71 % ) " "Info: Total interconnect delay = 4.616 ns ( 59.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.731 ns" { clk_48Mhz CLK_100HZ B2[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.731 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} B2[4] {} } { 0.000ns 0.000ns 0.762ns 3.854ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 7.749 ns - Longest register " "Info: - Longest clock path from clock \"clk_48Mhz\" to source register is 7.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns CLK_100HZ 2 REG LC_X26_Y10_N2 57 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X26_Y10_N2; Fanout = 57; REG Node = 'CLK_100HZ'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.697 ns" { clk_48Mhz CLK_100HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.872 ns) + CELL(0.711 ns) 7.749 ns BCD_3CAI\[0\] 3 REG LC_X24_Y11_N9 6 " "Info: 3: + IC(3.872 ns) + CELL(0.711 ns) = 7.749 ns; Loc. = LC_X24_Y11_N9; Fanout = 6; REG Node = 'BCD_3CAI\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.583 ns" { CLK_100HZ BCD_3CAI[0] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.20 % ) " "Info: Total cell delay = 3.115 ns ( 40.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.634 ns ( 59.80 % ) " "Info: Total interconnect delay = 4.634 ns ( 59.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.749 ns" { clk_48Mhz CLK_100HZ BCD_3CAI[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.749 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} BCD_3CAI[0] {} } { 0.000ns 0.000ns 0.762ns 3.872ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.731 ns" { clk_48Mhz CLK_100HZ B2[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.731 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} B2[4] {} } { 0.000ns 0.000ns 0.762ns 3.854ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.749 ns" { clk_48Mhz CLK_100HZ BCD_3CAI[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.749 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} BCD_3CAI[0] {} } { 0.000ns 0.000ns 0.762ns 3.872ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.507 ns" { BCD_3CAI[0] LessThan4~66 B2[7]~516 B2[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.507 ns" { BCD_3CAI[0] {} LessThan4~66 {} B2[7]~516 {} B2[4] {} } { 0.000ns 0.621ns 2.389ns 0.748ns } { 0.000ns 0.590ns 0.292ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.731 ns" { clk_48Mhz CLK_100HZ B2[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.731 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} B2[4] {} } { 0.000ns 0.000ns 0.762ns 3.854ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.749 ns" { clk_48Mhz CLK_100HZ BCD_3CAI[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.749 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_100HZ {} BCD_3CAI[0] {} } { 0.000ns 0.000ns 0.762ns 3.872ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "CLK_COUNT_100HZ\[18\] reset clk_48Mhz 7.492 ns register " "Info: tsu for register \"CLK_COUNT_100HZ\[18\]\" (data pin = \"reset\", clock pin = \"clk_48Mhz\") is 7.492 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.364 ns + Longest pin register " "Info: + Longest pin to register delay is 10.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_23 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 35; PIN Node = 'reset'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.028 ns) + CELL(0.867 ns) 10.364 ns CLK_COUNT_100HZ\[18\] 2 REG LC_X25_Y9_N8 4 " "Info: 2: + IC(8.028 ns) + CELL(0.867 ns) = 10.364 ns; Loc. = LC_X25_Y9_N8; Fanout = 4; REG Node = 'CLK_COUNT_100HZ\[18\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.895 ns" { reset CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 22.54 % ) " "Info: Total cell delay = 2.336 ns ( 22.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.028 ns ( 77.46 % ) " "Info: Total interconnect delay = 8.028 ns ( 77.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.364 ns" { reset CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.364 ns" { reset {} reset~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 8.028ns } { 0.000ns 1.469ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_48Mhz\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns CLK_COUNT_100HZ\[18\] 2 REG LC_X25_Y9_N8 4 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X25_Y9_N8; Fanout = 4; REG Node = 'CLK_COUNT_100HZ\[18\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { clk_48Mhz CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk_48Mhz CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.364 ns" { reset CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.364 ns" { reset {} reset~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 8.028ns } { 0.000ns 1.469ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk_48Mhz CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_48Mhz LCD_E LCD_E~reg0 14.294 ns register " "Info: tco from clock \"clk_48Mhz\" to destination pin \"LCD_E\" through register \"LCD_E~reg0\" is 14.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 7.414 ns + Longest register " "Info: + Longest clock path from clock \"clk_48Mhz\" to source register is 7.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N6 58 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N6; Fanout = 58; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.554 ns) + CELL(0.711 ns) 7.414 ns LCD_E~reg0 3 REG LC_X23_Y13_N5 2 " "Info: 3: + IC(3.554 ns) + CELL(0.711 ns) = 7.414 ns; Loc. = LC_X23_Y13_N5; Fanout = 2; REG Node = 'LCD_E~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.265 ns" { CLK_400HZ LCD_E~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.02 % ) " "Info: Total cell delay = 3.115 ns ( 42.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.299 ns ( 57.98 % ) " "Info: Total interconnect delay = 4.299 ns ( 57.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.414 ns" { clk_48Mhz CLK_400HZ LCD_E~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.414 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_400HZ {} LCD_E~reg0 {} } { 0.000ns 0.000ns 0.745ns 3.554ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.656 ns + Longest register pin " "Info: + Longest register to pin delay is 6.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCD_E~reg0 1 REG LC_X23_Y13_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y13_N5; Fanout = 2; REG Node = 'LCD_E~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCD_E~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.532 ns) + CELL(2.124 ns) 6.656 ns LCD_E 2 PIN PIN_50 0 " "Info: 2: + IC(4.532 ns) + CELL(2.124 ns) = 6.656 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'LCD_E'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.656 ns" { LCD_E~reg0 LCD_E } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 31.91 % ) " "Info: Total cell delay = 2.124 ns ( 31.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.532 ns ( 68.09 % ) " "Info: Total interconnect delay = 4.532 ns ( 68.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.656 ns" { LCD_E~reg0 LCD_E } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.656 ns" { LCD_E~reg0 {} LCD_E {} } { 0.000ns 4.532ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.414 ns" { clk_48Mhz CLK_400HZ LCD_E~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.414 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_400HZ {} LCD_E~reg0 {} } { 0.000ns 0.000ns 0.745ns 3.554ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.656 ns" { LCD_E~reg0 LCD_E } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.656 ns" { LCD_E~reg0 {} LCD_E {} } { 0.000ns 4.532ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}