prev_cmp_up3_clock.map.qmsg

测试人体视觉的反应时间

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "BCD_SECD1\[3\] data_in GND " "Warning (14130): Reduced register \"BCD_SECD1\[3\]\" with stuck data_in port to stuck value GND" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 244 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_ENABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently enabled" { { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[0\]~0 " "Warning: Node \"DATA_BUS\[0\]~0\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[1\]~1 " "Warning: Node \"DATA_BUS\[1\]~1\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[2\]~2 " "Warning: Node \"DATA_BUS\[2\]~2\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[3\]~3 " "Warning: Node \"DATA_BUS\[3\]~3\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[4\]~4 " "Warning: Node \"DATA_BUS\[4\]~4\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[5\]~5 " "Warning: Node \"DATA_BUS\[5\]~5\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Warning" "WOPT_MLS_NODE_NAME" "DATA_BUS\[7\]~7 " "Warning: Node \"DATA_BUS\[7\]~7\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "RESET_LED GND " "Warning (13410): Pin \"RESET_LED\" stuck at GND" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEC_LED GND " "Warning (13410): Pin \"SEC_LED\" stuck at GND" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "Q_LED GND " "Warning (13410): Pin \"Q_LED\" stuck at GND" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_RW GND " "Warning (13410): Pin \"LCD_RW\" stuck at GND" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 9 -1 0 } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 -1 0 } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 -1 0 } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 59 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "8 8 " "Info: 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[7\] " "Info: Register \"B2\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[6\] " "Info: Register \"B2\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[5\] " "Info: Register \"B2\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[4\] " "Info: Register \"B2\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[3\] " "Info: Register \"B2\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[0\] " "Info: Register \"B2\[0\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[1\] " "Info: Register \"B2\[1\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "B2\[2\] " "Info: Register \"B2\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "D " "Warning (15610): No output dependent on input pin \"D\"" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "237 " "Info: Implemented 237 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "212 " "Info: Implemented 212 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 34 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 23 11:16:26 2008 " "Info: Processing ended: Wed Jul 23 11:16:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}