up3_clock.hier_info

测试人体视觉的反应时间

|UP3_CLOCK
reset => process3~0.IN1
reset => Q~reg0.ACLR
reset => COUNT[0].ACLR
reset => COUNT[1].ACLR
reset => COUNT[2].ACLR
reset => COUNT[3].ACLR
reset => COUNT[4].ACLR
reset => COUNT[5].ACLR
reset => COUNT[6].ACLR
reset => COUNT[7].ACLR
reset => process1~0.IN1
reset => CLK_400HZ~1.OUTPUTSELECT
reset => CLK_COUNT_400HZ~39.OUTPUTSELECT
reset => CLK_COUNT_400HZ~38.OUTPUTSELECT
reset => CLK_COUNT_400HZ~37.OUTPUTSELECT
reset => CLK_COUNT_400HZ~36.OUTPUTSELECT
reset => CLK_COUNT_400HZ~35.OUTPUTSELECT
reset => CLK_COUNT_400HZ~34.OUTPUTSELECT
reset => CLK_COUNT_400HZ~33.OUTPUTSELECT
reset => CLK_COUNT_400HZ~32.OUTPUTSELECT
reset => CLK_COUNT_400HZ~31.OUTPUTSELECT
reset => CLK_COUNT_400HZ~30.OUTPUTSELECT
reset => CLK_COUNT_400HZ~29.OUTPUTSELECT
reset => CLK_COUNT_400HZ~28.OUTPUTSELECT
reset => CLK_COUNT_400HZ~27.OUTPUTSELECT
reset => CLK_COUNT_400HZ~26.OUTPUTSELECT
reset => CLK_COUNT_400HZ~25.OUTPUTSELECT
reset => CLK_COUNT_400HZ~24.OUTPUTSELECT
reset => CLK_COUNT_400HZ~23.OUTPUTSELECT
reset => CLK_COUNT_400HZ~22.OUTPUTSELECT
reset => CLK_COUNT_400HZ~21.OUTPUTSELECT
reset => CLK_COUNT_400HZ~20.OUTPUTSELECT
reset => CLK_100HZ.ENA
reset => CLK_COUNT_100HZ[0].ENA
reset => CLK_COUNT_100HZ[1].ENA
reset => CLK_COUNT_100HZ[2].ENA
reset => CLK_COUNT_100HZ[3].ENA
reset => CLK_COUNT_100HZ[4].ENA
reset => CLK_COUNT_100HZ[5].ENA
reset => CLK_COUNT_100HZ[6].ENA
reset => CLK_COUNT_100HZ[7].ENA
reset => CLK_COUNT_100HZ[8].ENA
reset => CLK_COUNT_100HZ[9].ENA
reset => CLK_COUNT_100HZ[10].ENA
reset => CLK_COUNT_100HZ[11].ENA
reset => CLK_COUNT_100HZ[12].ENA
reset => CLK_COUNT_100HZ[13].ENA
reset => CLK_COUNT_100HZ[14].ENA
reset => CLK_COUNT_100HZ[15].ENA
reset => CLK_COUNT_100HZ[16].ENA
reset => CLK_COUNT_100HZ[17].ENA
reset => CLK_COUNT_100HZ[18].ENA
reset => CLK_COUNT_100HZ[19].ENA
clk_48Mhz => CLK_COUNT_400HZ[19].CLK
clk_48Mhz => CLK_COUNT_400HZ[18].CLK
clk_48Mhz => CLK_COUNT_400HZ[17].CLK
clk_48Mhz => CLK_COUNT_400HZ[16].CLK
clk_48Mhz => CLK_COUNT_400HZ[15].CLK
clk_48Mhz => CLK_COUNT_400HZ[14].CLK
clk_48Mhz => CLK_COUNT_400HZ[13].CLK
clk_48Mhz => CLK_COUNT_400HZ[12].CLK
clk_48Mhz => CLK_COUNT_400HZ[11].CLK
clk_48Mhz => CLK_COUNT_400HZ[10].CLK
clk_48Mhz => CLK_COUNT_400HZ[9].CLK
clk_48Mhz => CLK_COUNT_400HZ[8].CLK
clk_48Mhz => CLK_COUNT_400HZ[7].CLK
clk_48Mhz => CLK_COUNT_400HZ[6].CLK
clk_48Mhz => CLK_COUNT_400HZ[5].CLK
clk_48Mhz => CLK_COUNT_400HZ[4].CLK
clk_48Mhz => CLK_COUNT_400HZ[3].CLK
clk_48Mhz => CLK_COUNT_400HZ[2].CLK
clk_48Mhz => CLK_COUNT_400HZ[1].CLK
clk_48Mhz => CLK_COUNT_400HZ[0].CLK
clk_48Mhz => CLK_400HZ.CLK
clk_48Mhz => CLK_COUNT_100HZ[19].CLK
clk_48Mhz => CLK_COUNT_100HZ[18].CLK
clk_48Mhz => CLK_COUNT_100HZ[17].CLK
clk_48Mhz => CLK_COUNT_100HZ[16].CLK
clk_48Mhz => CLK_COUNT_100HZ[15].CLK
clk_48Mhz => CLK_COUNT_100HZ[14].CLK
clk_48Mhz => CLK_COUNT_100HZ[13].CLK
clk_48Mhz => CLK_COUNT_100HZ[12].CLK
clk_48Mhz => CLK_COUNT_100HZ[11].CLK
clk_48Mhz => CLK_COUNT_100HZ[10].CLK
clk_48Mhz => CLK_COUNT_100HZ[9].CLK
clk_48Mhz => CLK_COUNT_100HZ[8].CLK
clk_48Mhz => CLK_COUNT_100HZ[7].CLK
clk_48Mhz => CLK_COUNT_100HZ[6].CLK
clk_48Mhz => CLK_COUNT_100HZ[5].CLK
clk_48Mhz => CLK_COUNT_100HZ[4].CLK
clk_48Mhz => CLK_COUNT_100HZ[3].CLK
clk_48Mhz => CLK_COUNT_100HZ[2].CLK
clk_48Mhz => CLK_COUNT_100HZ[1].CLK
clk_48Mhz => CLK_COUNT_100HZ[0].CLK
clk_48Mhz => CLK_100HZ.CLK
D => ~NO_FANOUT~
K => process2~0.IN1
K => process1~1.IN1
K => B2~0.OUTPUTSELECT
K => B2~1.OUTPUTSELECT
K => B2~2.OUTPUTSELECT
K => B2~3.OUTPUTSELECT
K => B2~4.OUTPUTSELECT
K => B2~5.OUTPUTSELECT
K => B2~6.OUTPUTSELECT
K => B2~7.OUTPUTSELECT
K => Q_LED~5.OUTPUTSELECT
K => RESET_LED~5.OUTPUTSELECT
K => SEC_LED~4.OUTPUTSELECT
K => B2~15.OUTPUTSELECT
K => B2~14.OUTPUTSELECT
K => B2~13.OUTPUTSELECT
K => B2~12.OUTPUTSELECT
K => B2~11.OUTPUTSELECT
K => B2~10.OUTPUTSELECT
K => B2~9.OUTPUTSELECT
K => B2~8.OUTPUTSELECT
D3 => SEC_LED~3.OUTPUTSELECT
D3 => RESET_LED~4.OUTPUTSELECT
D3 => Q_LED~4.OUTPUTSELECT
D3 => COUNT2~5.OUTPUTSELECT
D3 => COUNT2~4.OUTPUTSELECT
D3 => COUNT2~3.OUTPUTSELECT
D3 => COUNT2~2.OUTPUTSELECT
D3 => COUNT2~1.OUTPUTSELECT
D3 => COUNT2~0.OUTPUTSELECT
D4 => process4~0.IN1
LCD_RS <= LCD_RS~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_E <= LCD_E~reg0.DB_MAX_OUTPUT_PORT_TYPE
RESET_LED <= RESET_LED~reg0.DB_MAX_OUTPUT_PORT_TYPE
SEC_LED <= SEC_LED~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q_LED <= Q_LED~reg0.DB_MAX_OUTPUT_PORT_TYPE
LCD_RW <= LCD_RW~reg0.DB_MAX_OUTPUT_PORT_TYPE
Q <= Q~reg0.DB_MAX_OUTPUT_PORT_TYPE
DATA_BUS[0] <= DATA_BUS[0]~0
DATA_BUS[1] <= DATA_BUS[1]~1
DATA_BUS[2] <= DATA_BUS[2]~2
DATA_BUS[3] <= DATA_BUS[3]~3
DATA_BUS[4] <= DATA_BUS[4]~4
DATA_BUS[5] <= DATA_BUS[5]~5
DATA_BUS[6] <= DATA_BUS[6]~6
DATA_BUS[7] <= DATA_BUS[7]~7
SW3[0] => Equal0.IN15
SW3[1] => Equal0.IN14
SW3[2] => Equal0.IN13
SW3[3] => Equal0.IN12