prev_cmp_up3_clock.tan.qmsg

测试人体视觉的反应时间

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_100HZ " "Info: Detected ripple clock \"CLK_100HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_100HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_48Mhz register CLK_COUNT_100HZ\[7\] register CLK_COUNT_100HZ\[9\] 181.03 MHz 5.524 ns Internal " "Info: Clock \"clk_48Mhz\" has Internal fmax of 181.03 MHz between source register \"CLK_COUNT_100HZ\[7\]\" and destination register \"CLK_COUNT_100HZ\[9\]\" (period= 5.524 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.263 ns + Longest register register " "Info: + Longest register to register delay is 5.263 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLK_COUNT_100HZ\[7\] 1 REG LC_X27_Y12_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y12_N7; Fanout = 4; REG Node = 'CLK_COUNT_100HZ\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_COUNT_100HZ[7] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.590 ns) 1.855 ns LessThan1~387 2 COMB LC_X27_Y10_N2 1 " "Info: 2: + IC(1.265 ns) + CELL(0.590 ns) = 1.855 ns; Loc. = LC_X27_Y10_N2; Fanout = 1; COMB Node = 'LessThan1~387'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.855 ns" { CLK_COUNT_100HZ[7] LessThan1~387 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.151 ns LessThan1~388 3 COMB LC_X27_Y10_N3 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.151 ns; Loc. = LC_X27_Y10_N3; Fanout = 1; COMB Node = 'LessThan1~388'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan1~387 LessThan1~388 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.447 ns LessThan1~389 4 COMB LC_X27_Y10_N4 1 " "Info: 4: + IC(0.182 ns) + CELL(0.114 ns) = 2.447 ns; Loc. = LC_X27_Y10_N4; Fanout = 1; COMB Node = 'LessThan1~389'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan1~388 LessThan1~389 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.114 ns) 2.901 ns LessThan1~390 5 COMB LC_X27_Y10_N5 21 " "Info: 5: + IC(0.340 ns) + CELL(0.114 ns) = 2.901 ns; Loc. = LC_X27_Y10_N5; Fanout = 21; COMB Node = 'LessThan1~390'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { LessThan1~389 LessThan1~390 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(1.112 ns) 5.263 ns CLK_COUNT_100HZ\[9\] 6 REG LC_X27_Y12_N9 3 " "Info: 6: + IC(1.250 ns) + CELL(1.112 ns) = 5.263 ns; Loc. = LC_X27_Y12_N9; Fanout = 3; REG Node = 'CLK_COUNT_100HZ\[9\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.362 ns" { LessThan1~390 CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.044 ns ( 38.84 % ) " "Info: Total cell delay = 2.044 ns ( 38.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.219 ns ( 61.16 % ) " "Info: Total interconnect delay = 3.219 ns ( 61.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.263 ns" { CLK_COUNT_100HZ[7] LessThan1~387 LessThan1~388 LessThan1~389 LessThan1~390 CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.263 ns" { CLK_COUNT_100HZ[7] {} LessThan1~387 {} LessThan1~388 {} LessThan1~389 {} LessThan1~390 {} CLK_COUNT_100HZ[9] {} } { 0.000ns 1.265ns 0.182ns 0.182ns 0.340ns 1.250ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_48Mhz\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns CLK_COUNT_100HZ\[9\] 2 REG LC_X27_Y12_N9 3 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y12_N9; Fanout = 3; REG Node = 'CLK_COUNT_100HZ\[9\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk_48Mhz CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[9] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk_48Mhz\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns CLK_COUNT_100HZ\[7\] 2 REG LC_X27_Y12_N7 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y12_N7; Fanout = 4; REG Node = 'CLK_COUNT_100HZ\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk_48Mhz CLK_COUNT_100HZ[7] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[7] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[9] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[7] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.263 ns" { CLK_COUNT_100HZ[7] LessThan1~387 LessThan1~388 LessThan1~389 LessThan1~390 CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.263 ns" { CLK_COUNT_100HZ[7] {} LessThan1~387 {} LessThan1~388 {} LessThan1~389 {} LessThan1~390 {} CLK_COUNT_100HZ[9] {} } { 0.000ns 1.265ns 0.182ns 0.182ns 0.340ns 1.250ns } { 0.000ns 0.590ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[9] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[9] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[7] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "CLK_COUNT_100HZ\[18\] reset clk_48Mhz 7.424 ns register " "Info: tsu for register \"CLK_COUNT_100HZ\[18\]\" (data pin = \"reset\", clock pin = \"clk_48Mhz\") is 7.424 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.329 ns + Longest pin register " "Info: + Longest pin to register delay is 10.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_23 35 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 35; PIN Node = 'reset'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.993 ns) + CELL(0.867 ns) 10.329 ns CLK_COUNT_100HZ\[18\] 2 REG LC_X27_Y11_N8 4 " "Info: 2: + IC(7.993 ns) + CELL(0.867 ns) = 10.329 ns; Loc. = LC_X27_Y11_N8; Fanout = 4; REG Node = 'CLK_COUNT_100HZ\[18\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.860 ns" { reset CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 22.62 % ) " "Info: Total cell delay = 2.336 ns ( 22.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.993 ns ( 77.38 % ) " "Info: Total interconnect delay = 7.993 ns ( 77.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.329 ns" { reset CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.329 ns" { reset {} reset~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 7.993ns } { 0.000ns 1.469ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_48Mhz\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns CLK_COUNT_100HZ\[18\] 2 REG LC_X27_Y11_N8 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y11_N8; Fanout = 4; REG Node = 'CLK_COUNT_100HZ\[18\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk_48Mhz CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.329 ns" { reset CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.329 ns" { reset {} reset~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 7.993ns } { 0.000ns 1.469ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk_48Mhz CLK_COUNT_100HZ[18] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_COUNT_100HZ[18] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_48Mhz Q Q~reg0 13.914 ns register " "Info: tco from clock \"clk_48Mhz\" to destination pin \"Q\" through register \"Q~reg0\" is 13.914 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 7.408 ns + Longest register " "Info: + Longest clock path from clock \"clk_48Mhz\" to source register is 7.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 42 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 42; CLK Node = 'clk_48Mhz'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_48Mhz } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns CLK_400HZ 2 REG LC_X8_Y10_N9 58 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 58; REG Node = 'CLK_400HZ'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.548 ns) + CELL(0.711 ns) 7.408 ns Q~reg0 3 REG LC_X19_Y13_N9 1 " "Info: 3: + IC(3.548 ns) + CELL(0.711 ns) = 7.408 ns; Loc. = LC_X19_Y13_N9; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.259 ns" { CLK_400HZ Q~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 373 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.05 % ) " "Info: Total cell delay = 3.115 ns ( 42.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.293 ns ( 57.95 % ) " "Info: Total interconnect delay = 4.293 ns ( 57.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk_48Mhz CLK_400HZ Q~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_400HZ {} Q~reg0 {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 373 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.282 ns + Longest register pin " "Info: + Longest register to pin delay is 6.282 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q~reg0 1 REG LC_X19_Y13_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y13_N9; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q~reg0 } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 373 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.158 ns) + CELL(2.124 ns) 6.282 ns Q 2 PIN PIN_55 0 " "Info: 2: + IC(4.158 ns) + CELL(2.124 ns) = 6.282 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'Q'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.282 ns" { Q~reg0 Q } "NODE_NAME" } } { "UP3_CLOCK.vhd" "" { Text "D:/实验5-时钟设计11/UP3_CLOCK.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 33.81 % ) " "Info: Total cell delay = 2.124 ns ( 33.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.158 ns ( 66.19 % ) " "Info: Total interconnect delay = 4.158 ns ( 66.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.282 ns" { Q~reg0 Q } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.282 ns" { Q~reg0 {} Q {} } { 0.000ns 4.158ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { clk_48Mhz CLK_400HZ Q~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.408 ns" { clk_48Mhz {} clk_48Mhz~out0 {} CLK_400HZ {} Q~reg0 {} } { 0.000ns 0.000ns 0.745ns 3.548ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.282 ns" { Q~reg0 Q } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.282 ns" { Q~reg0 {} Q {} } { 0.000ns 4.158ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}