counter_4_bit.tan.rpt

非常有参考价值的 计数器 源代码

+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                   ;
+-------+----------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)             ; From                                  ; To                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[0] ; lpm_counter:counter_out_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[1] ; lpm_counter:counter_out_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[2] ; lpm_counter:counter_out_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[3] ; lpm_counter:counter_out_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[0] ; lpm_counter:counter_out_rtl_0|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[1] ; lpm_counter:counter_out_rtl_0|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[2] ; lpm_counter:counter_out_rtl_0|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[0] ; lpm_counter:counter_out_rtl_0|dffs[1] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[1] ; lpm_counter:counter_out_rtl_0|dffs[1] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
; N/A   ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:counter_out_rtl_0|dffs[0] ; lpm_counter:counter_out_rtl_0|dffs[0] ; clk        ; clk      ; None                        ; None                      ; 3.600 ns                ;
+-------+----------------------------------+---------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------+
; tco                                                                                                     ;
+-------+--------------+------------+---------------------------------------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From                                  ; To             ; From Clock ;
+-------+--------------+------------+---------------------------------------+----------------+------------+
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[3] ; counter_out[3] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[2] ; counter_out[2] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[1] ; counter_out[1] ; clk        ;
; N/A   ; None         ; 2.800 ns   ; lpm_counter:counter_out_rtl_0|dffs[0] ; counter_out[0] ; clk        ;
+-------+--------------+------------+---------------------------------------+----------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Jul 17 11:25:42 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off counter_4_bit -c counter_4_bit
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 175.44 MHz between source register "lpm_counter:counter_out_rtl_0|dffs[0]" and destination register "lpm_counter:counter_out_rtl_0|dffs[3]" (period= 5.7 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[0]'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[3]'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[3]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[0]'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
Info: tco from clock "clk" to destination pin "counter_out[3]" through register "lpm_counter:counter_out_rtl_0|dffs[3]" is 2.800 ns
    Info: + Longest clock path from clock "clk" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[3]'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0|dffs[3]'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'counter_out[3]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jul 17 11:25:43 2006
    Info: Elapsed time: 00:00:02