counter_4_bit.v

来自「非常有参考价值的 计数器 源代码」· Verilog 代码 · 共 16 行

module  counter_4_bit(clk,counter_out);

output [3:0] counter_out;
input  clk;

reg  [3:0] counter_out;

always  @(posedge clk)
begin
  if (counter_out == 4'b1111)
	counter_out <= 4'b0000;
  else
	counter_out <= counter_out + 4'b0001;
end
endmodule