📄 counter_4_bit.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "counter_4_bit.v" "" { Text "E:/戴仙金/资料/Verilog书/counter_4_bit/counter_4_bit.v" 4 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:counter_out_rtl_0\|dffs\[0\] register lpm_counter:counter_out_rtl_0\|dffs\[3\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 175.44 MHz between source register \"lpm_counter:counter_out_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:counter_out_rtl_0\|dffs\[3\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:counter_out_rtl_0\|dffs\[0\] 1 REG LC1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "" { lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns lpm_counter:counter_out_rtl_0\|dffs\[3\] 2 REG LC5 2 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "3.600 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "3.600 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "" { clk } "NODE_NAME" } "" } } { "counter_4_bit.v" "" { Text "E:/戴仙金/资料/Verilog书/counter_4_bit/counter_4_bit.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:counter_out_rtl_0\|dffs\[3\] 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "0.100 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "" { clk } "NODE_NAME" } "" } } { "counter_4_bit.v" "" { Text "E:/戴仙金/资料/Verilog书/counter_4_bit/counter_4_bit.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:counter_out_rtl_0\|dffs\[0\] 2 REG LC1 5 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "0.100 ns" { clk lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "3.600 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk counter_out\[3\] lpm_counter:counter_out_rtl_0\|dffs\[3\] 2.800 ns register " "Info: tco from clock \"clk\" to destination pin \"counter_out\[3\]\" through register \"lpm_counter:counter_out_rtl_0\|dffs\[3\]\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns clk 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'clk'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "" { clk } "NODE_NAME" } "" } } { "counter_4_bit.v" "" { Text "E:/戴仙金/资料/Verilog书/counter_4_bit/counter_4_bit.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:counter_out_rtl_0\|dffs\[3\] 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "0.100 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:counter_out_rtl_0\|dffs\[3\] 1 REG LC5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "" { lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns counter_out\[3\] 2 PIN PIN_8 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'counter_out\[3\]'" { } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[3] counter_out[3] } "NODE_NAME" } "" } } { "counter_4_bit.v" "" { Text "E:/戴仙金/资料/Verilog书/counter_4_bit/counter_4_bit.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[3] counter_out[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[3] counter_out[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } } } 0} } { { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "1.300 ns" { clk lpm_counter:counter_out_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { clk clk~out lpm_counter:counter_out_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit_cmp.qrpt" Compiler "counter_4_bit" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/counter_4_bit/db/counter_4_bit.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/counter_4_bit/" "" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[3] counter_out[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[3] counter_out[3] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 11:25:43 2006 " "Info: Processing ended: Mon Jul 17 11:25:43 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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