fen2.vhd

来自「在软件MAX+plus II环境中」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FEN2 IS
PORT(
    M5_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    LED_B,BS_B: IN STD_LOGIC;
    OUT_PUT,OUT_M3:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END FEN2;
ARCHITECTURE A OF FEN2 IS
BEGIN
  PROCESS(LED_B,BS_B)
    BEGIN
      IF(LED_B='0' AND BS_B='0') THEN  
         OUT_PUT<=M5_IN;
       
      ELSE 
         OUT_M3<=M5_IN; 
      END IF;
  END PROCESS;
END A;