ls74.vhd

来自「在软件MAX+plus II环境中」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY LS74 IS
PORT(
     LDFR:IN STD_LOGIC;
     CY,ZI:IN STD_LOGIC;
     FC,FZ:OUT STD_LOGIC
    );
END LS74;
ARCHITECTURE A OF LS74 IS
BEGIN
  PROCESS(LDFR)
  BEGIN
    IF(LDFR'EVENT AND LDFR='1') THEN 
      FC<=CY;
      FZ<=ZI;
    END IF;
  END PROCESS;
END A;