alu.vhd

来自「在软件MAX+plus II环境中」· VHDL 代码 · 共 69 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ALU IS
PORT(
       AC, DR: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       S1, S0: IN STD_LOGIC;
       BCDOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       CY,ZI:  OUT STD_LOGIC
       );
END ALU;
ARCHITECTURE A OF ALU IS
SIGNAL AA,BB,TEMP: STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
       PROCESS(S1,S0)  
       BEGIN
          IF(S1='0' AND S0='0') THEN               
            AA<='0'&AC;
            BB<='0'&DR;
            TEMP <= AA + BB;
            BCDOUT <= TEMP(7 DOWNTO 0);  --AC + DR;
            CY<=TEMP(8);
                IF( TEMP ="100000000") THEN
                    ZI <= '1';
                ELSE
                    ZI <= '0';
                END IF;
          ELSIF(S1='0' AND S0='1') THEN  --执行比较或减运算
          
            AA<='0'&AC;
            BB<='0'&DR;
            TEMP <= AA - BB;
            BCDOUT <= TEMP(7 DOWNTO 0);
            CY<=TEMP(8);
            IF( TEMP ="000000000") THEN
               ZI <= '1';
            ELSE
               ZI <= '0';
            END IF;
          ELSIF(S1='1' AND S0='0') THEN --加1运算
            AA<='0'&AC;
            TEMP<=AA+1;
            BCDOUT<=TEMP(7 DOWNTO 0);
            CY<=TEMP(8);
            IF( TEMP ="100000000") THEN
               ZI <= '1';
            ELSE
               ZI <= '0';
            END IF;
          ELSIF(S1='1' AND S0='1') THEN--减一运算
            AA<='0'&AC;
            TEMP<=AA-1;
            BCDOUT<=TEMP(7 DOWNTO 0);
            CY<=TEMP(8);
            IF( TEMP ="000000000") THEN
                ZI <= '1';
            ELSE
                ZI <= '0';
            END IF;
          ELSE
            BCDOUT <= "00000000";
            CY <= '0';
            ZI <= '0';
          END IF;
       END PROCESS;
END A;