mux3.vhd

来自「在软件MAX+plus II环境中」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX3 IS
PORT(
     ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     SW_B,CS_B:IN STD_LOGIC;
     IFEN2,IM2_2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     M3OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END MUX3;
ARCHITECTURE A OF MUX3 IS
BEGIN
PROCESS(SW_B,CS_B)
  BEGIN
    IF(SW_B='0') THEN
      M3OUT<=ID;
    ELSIF( CS_B='0') THEN
      M3OUT<=IM2_2;
    ELSE
     M3OUT<=IFEN2;
    END IF;
  END PROCESS;
END A;