mcu8951.map.qmsg

KX_DVP3F型FPGA应用板/开发板（全套）包括： &#61592 CycloneII系列FPGA EP2C8Q208C8 40万们

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 21 13:59:57 2008 " "Info: Processing started: Thu Feb 21 13:59:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MCU8951 -c MCU8951 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MCU8951 -c MCU8951" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/IRAM.VHD " "Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/IRAM.VHD is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ROM4K.VHD " "Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ROM4K.VHD is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/reg8b.vhd " "Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/reg8b.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ETESTER.VHD " "Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ETESTER.VHD is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/reg4b.vhd " "Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/reg4b.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DECODR.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DECODR.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DECODR-one " "Info: Found design unit 1: DECODR-one" {  } { { "DECODR.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/DECODR.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DECODR " "Info: Found entity 1: DECODR" {  } { { "DECODR.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/DECODR.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CNT4B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CNT4B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CNT4B-DACC " "Info: Found design unit 1: CNT4B-DACC" {  } { { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CNT4B " "Info: Found entity 1: CNT4B" {  } { { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "MCU8951.bdf 1 1 " "Warning: Using design file MCU8951.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 MCU8951 " "Info: Found entity 1: MCU8951" {  } { { "MCU8951.bdf" "" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "MCU8951 " "Info: Elaborating entity \"MCU8951\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CNT4B CNT4B:inst15 " "Info: Elaborating entity \"CNT4B\" for hierarchy \"CNT4B:inst15\"" {  } { { "MCU8951.bdf" "inst15" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -1152 864 992 -1056 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "REG32B.vhd 2 1 " "Warning: Using design file REG32B.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG32B-behav " "Info: Found design unit 1: REG32B-behav" {  } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG32B " "Info: Found entity 1: REG32B" {  } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG32B REG32B:inst12 " "Info: Elaborating entity \"REG32B\" for hierarchy \"REG32B:inst12\"" {  } { { "MCU8951.bdf" "inst12" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -944 872 1040 -848 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pll2.vhd 2 1 " "Warning: Using design file pll2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll2-SYN " "Info: Found design unit 1: pll2-SYN" {  } { { "pll2.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/pll2.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll2 " "Info: Found entity 1: pll2" {  } { { "pll2.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/pll2.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll2 pll2:inst13 " "Info: Elaborating entity \"pll2\" for hierarchy \"pll2:inst13\"" {  } { { "MCU8951.bdf" "inst13" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -1104 424 664 -944 "inst13" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll2:inst13\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll2:inst13\|altpll:altpll_component\"" {  } { { "pll2.vhd" "altpll_component" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/pll2.vhd" 129 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pll2:inst13\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll2:inst13\|altpll:altpll_component\"" {  } { { "pll2.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/pll2.vhd" 129 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "ADDER32B.vhd 2 1 " "Warning: Using design file ADDER32B.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER32B-behav " "Info: Found design unit 1: ADDER32B-behav" {  } { { "ADDER32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ADDER32B.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER32B " "Info: Found entity 1: ADDER32B" {  } { { "ADDER32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ADDER32B.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER32B ADDER32B:inst11 " "Info: Elaborating entity \"ADDER32B\" for hierarchy \"ADDER32B:inst11\"" {  } { { "MCU8951.bdf" "inst11" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -928 712 840 -832 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "CC.vhd 4 2 " "Warning: Using design file CC.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CC_lpm_constant_lm8-RTL " "Info: Found design unit 1: CC_lpm_constant_lm8-RTL" {  } { { "CC.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CC.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 cc-RTL " "Info: Found design unit 2: cc-RTL" {  } { { "CC.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CC.vhd" 73 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CC_lpm_constant_lm8 " "Info: Found entity 1: CC_lpm_constant_lm8" {  } { { "CC.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CC.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 CC " "Info: Found entity 2: CC" {  } { { "CC.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CC.vhd" 65 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CC CC:inst14 " "Info: Elaborating entity \"CC\" for hierarchy \"CC:inst14\"" {  } { { "MCU8951.bdf" "inst14" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -904 552 616 -856 "inst14" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CC_lpm_constant_lm8 CC:inst14\|CC_lpm_constant_lm8:CC_lpm_constant_lm8_component " "Info: Elaborating entity \"CC_lpm_constant_lm8\" for hierarchy \"CC:inst14\|CC_lpm_constant_lm8:CC_lpm_constant_lm8_component\"" {  } { { "CC.vhd" "CC_lpm_constant_lm8_component" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CC.vhd" 90 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "REG32B:inst12\|DOUT\[0\] data_in GND " "Warning: Reduced register \"REG32B:inst12\|DOUT\[0\]\" with stuck data_in port to stuck value GND" {  } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "REG32B:inst12\|DOUT\[1\] data_in GND " "Warning: Reduced register \"REG32B:inst12\|DOUT\[1\]\" with stuck data_in port to stuck value GND" {  } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "65 " "Info: Implemented 65 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "38 " "Info: Implemented 38 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 21 14:00:00 2008 " "Info: Processing ended: Thu Feb 21 14:00:00 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}